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HMS30C7210 arm based 32-bit microprocessor datasheet (7210 ds-07) copyright. 2004 magnachip semiconductor ltd. all rights reserved. no part of this publication may be copied in any form, by photocopy, microfilm, retrieval system, or by an y other means now known or hereafter invented without the prior written permission of magnachip semiconductor ltd. magnachip semiconductor ltd. #1, hyangjeong-dong, heungduk-gu, cheongju-si, chungcheongbuk-do, republic of korea homepage: www.magnachip.com technical support homepage: www.softonchip.com h.q. of magnachip semiconductor ltd. marketing site sales in korea telephone: 82-(0)43-270-4070 telephone: 82-(0)43-270-4085 telephone: 82-(0)2-3459-3738 facsimile: 82-(0)43-270-4099 facsimile: 82-(0)43-270-4099 facsimile: 82-(0)2-3459-3945 world wide sales network u.s.a. taiwan hong kong telephone: 1-408-232-8757 telephone: 886-(0)2-2500-8357 telephone: 852-2971-1640 facsimile: 1-408-232-8135 facsimile: 886-(0)2-2509-8977 facsimile: 852-2971-1622
proprietary notice magnachip logo is trademark of magnachip semiconductor ltd. neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or re produced in any material from except with the prior permission of the copyright holder. the product described in this document is subject to continuous developments and improvements. all particulars of the product a nd its use contained in this document are given by magnachip in good faith. however, all warranties implied or expressed, including but not limited to implied warranties or merchantability, or fitness for purpose, are excluded. this document is intended only to assist the reader in the use of the product. magnachip semiconductor ltd. shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product. magnachip semiconductor ltd. may make changes to specification and product description at any time without notice. change log issue date by change a-01 2004/02/23 injae koo the first draft a-02 2004/07/05 hyerim chung adc / lcd / rtc / sci / sdram / ssi / timer / uart / usb add electrical characteristics a-03 2004/10/04 hyerim chung smi / uart / sci / keyboard / pin description / electrical characteristics a-04 2004/12/14 hyerim chung matrix keyboard interface controller a-05 2005/01/13 hyerim chung uart p82 interrupt identification register table a-06 2005/01/25 hyerim chung timer & pwm / matrix keyboard interface controller ds-07 2005/03/22 hyun-il kim change datasheet style and adding contents
introduction magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) i overview the HMS30C7210 is a highly integrated low power microprocessor for card reader system, and other applications described below. the device incorporates an arm720t cpu and system interface logic to interface with various types of devices. HMS30C7210 is a highly modular design based on the amba bus architecture between cpu and internal modules. the on-chip peripherals include lcd controller with dma support for internal sram and external sdram memory, analog functions such as adc and pll. intelligent interrupt controller and internal 8kbytes sram can support an efficient interrupt service execution. the HMS30C7210 also supports a touch panel interface. uart and usb provide serial communication channels for external systems. the power management features result in very low power consumption. the HMS30C7210 provides an excellent solution for card reader system. features 32-bit arm7tdmi risc static cmos cpu core (running up to 60 mhz) 8kbytes combined instruction/data cache memory management unit supports little-endian operating system 8kbytes sram for internal buffer memory 2kbytes boot rom on-chip peripherals with individual power-down: ? memory controller for rom(x8,16), flash(x8,16), sram(x8,16), sdram(x16) ? 5-state power management unit (sofrware selectable clock frequency) ? interrupt controller ? lcd controller for color and mono stn ? usb 1.1(slave) ? two smart card interface (uart 0,1) ? two uart (uart 2,3) ? one sir support uart (uart4) ? one modem support uart (uart5) ? four 16-bit timer channels (with output port) ? two 16-bit pwm channels (with output port) ? programmable watchdog timer with on-chip oscillator ? real-time clock (32.768khz oscillator) with separated vcc ? matrix keyboard control interface (6x6) ? 97 programmable gpio ? one 2-wire serial bus interface ? 2-channel master/slave ssi (spi) ? smc card interface ? on-chip 3-channel 10-bit adc jtag debug interface and boundary scan 0.35um cmos process 3.3v supply voltage 208-pin lqfp / cabga package low power consumption
introduction magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) ii HMS30C7210 system overview 6mhz 32.768khz apb bridge asb (30mhz) sdram controller sram (8kb) lcd controller boot rom (2kb) addr data (rtc) 60mhz (cpu) 30mhz (bus) uarts ssi(spi) wdt intc timer / pwm gpio static memory interface jtag tic arm720t (ice and boundary scan) osc osc pmu usb 2-wire sbi rtc 3-ch adc keyboard 48mhz (usb) smartcard smc addr data HMS30C7210 pll / 2 pll apb (low frequency) external device rom mono/color stn 640 x 480 max. host pc sdram sir (115.2kbps) battery touch panel rs232 smc matrix keyboard
contents magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) i list of contents 1 architectural ov erview ............................................................................ - 9 - 1.1 p rocessor ..................................................................................................................- 9 - 1.2 v ideo ..........................................................................................................................- 9 - 1.3 m emory ......................................................................................................................- 9 - 1.4 i nternal b us s tructure ..........................................................................................- 9 - 1.4.1 asb ......................................................................................................................... - 9 - 1.4.2 video bus................................................................................................................. - 9 - 1.4.3 apb ........................................................................................................................- 10 - 1.5 sdram c ontroller ............................................................................................... - 10 - 1.6 p eripherals ............................................................................................................. - 10 - 1.7 p ower management ................................................................................................ - 11 - 1.7.1 clock gating ...........................................................................................................- 11 - 1.7.2 pmu.......................................................................................................................- 11 - 1.8 t est and debug ........................................................................................................ - 12 - 2 signal description ..........................................................................................- 13 - 2.1 208-p in d iagram ...................................................................................................... - 13 - 2.2 208 p in / b all n ame ................................................................................................. - 14 - 2.2.1 lqfp type dimensions..........................................................................................- 15 - 2.2.2 cabga type dimensions.......................................................................................- 16 - 2.3 p in d escriptions ...................................................................................................... - 18 - 2.3.1 external signal functions......................................................................................- 18 - 2.3.2 pin specific description.........................................................................................- 21 - 3 arm720t macroc ell ........................................................................................- 25 - 3.1 arm720t m acrocell ............................................................................................. - 25 - 4 memory map.........................................................................................................- 27 - 5 internal boot rom..........................................................................................- 33 - 5.1 h ardware s etting .................................................................................................. - 33 - 5.2 s oftware s etting .................................................................................................... - 34 - 6 pmu & pll ...............................................................................................................- 37 - 6.1 e xternal s ignals ................................................................................................... - 38 - 6.2 r egisters ................................................................................................................. - 38 - 6.2.1 pmu mode register (pmumr).............................................................................- 39 - 6.2.2 pmu id register (pmuid) ...................................................................................- 39 - 6.2.3 pmu reset/status register (pmursr) .................................................................- 40 - 6.2.4 pmu clock control register (pmuccr) .............................................................- 43 - 6.2.5 pmu debounce counter test register (pmudctr) ............................................- 45 - 6.2.6 pmu test register (pmutr).................................................................................- 47 - 6.3 pmu f unctions ....................................................................................................... - 48 - 6.4 p ower m anagement ............................................................................................... - 51 - 6.4.1 state diagram ........................................................................................................- 51 - 6.4.2 power management states......................................................................................- 52 - 6.4.3 wake-up debounce and interrupt ..........................................................................- 53 - 6.5 r eset s equences ..................................................................................................... - 54 - 6.5.1 power on reset (cold reset)) ...............................................................................- 54 - 6.5.2 software generated warm reset ............................................................................- 56 - 6.5.3 an externally generated warm rese .....................................................................- 57 - 7 sdram contro ller..........................................................................................- 59 -
contents magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) ii 7.1 s upported m emory d evices ................................................................................... - 60 - 7.2 e xternal s ignals ................................................................................................... - 61 - 7.3 r egisters ................................................................................................................. - 61 - 7.3.1 sdram controller configuration register (sdcon)...........................................- 62 - 7.3.2 sdram controller refresh timer register (sdref) ............................................- 64 - 7.3.3 sdram controller write buffer flush timer register (sdwbf) ............................- 64 - 7.4 p ower - up i nitialization of the sdram s .............................................................. - 65 - 7.5 sdram m emory m ap ............................................................................................. - 66 - 7.6 amba a ccesses and a rbitration ......................................................................... - 69 - 7.7 m erging w rite b uffer ........................................................................................... - 70 - 8 static memory interface............................................................................- 73 - 8.1 e xternal s ignals ................................................................................................... - 74 - 8.2 r egisters ................................................................................................................. - 74 - 8.2.1 mem configuration register.................................................................................- 75 - 8.3 f unctional d escription ......................................................................................... - 76 - 8.3.1 memory bank select ...............................................................................................- 76 - 8.3.2 access sequencing..................................................................................................- 76 - 8.3.3 wait states generation ............................................................................................- 76 - 8.3.4 burst read control ..................................................................................................- 76 - 8.3.5 byte lane write control ...........................................................................................- 77 - 8.4 r ead , w rite t iming d iagram for e xternal m emory ......................................... - 80 - 8.4.1 read access timing (single mode).........................................................................- 80 - 8.4.2 read access timing (burst mode) .......................................................................- 81 - 8.4.3 write access timing ...............................................................................................- 82 - 9 amba peripherals ............................................................................................- 83 - 9.1 lcd controller................................................................................................ - 85 - 9.1.1 external signals .....................................................................................................- 86 - 9.1.2 registers.................................................................................................................- 86 - 9.1.3 lcd controller datapath........................................................................................- 94 - 9.1.4 color/grayscale dithering .....................................................................................- 95 - 9.1.5 lcd panel dependent settings................................................................................- 96 - 9.1.6 frame data dependen t settings ............................................................................- 103 - 9.1.7 other settings .......................................................................................................- 105 - 9.2 i nterrupt c ontroller ......................................................................................... - 107 - 9.2.1 registers...............................................................................................................- 108 - 9.2.2 interrupt control.................................................................................................. - 111 - 9.3 usb s lave i nterface ............................................................................................ - 113 - 9.3.1 block diagram .....................................................................................................- 114 - 9.3.2 external signals ...................................................................................................- 115 - 9.3.3 registers...............................................................................................................- 115 - 9.3.4 theory of operation.............................................................................................- 122 - 9.3.5 endpoint fifos (rx, tx)......................................................................................- 125 - 9.4 adc i nterface c ontroller ................................................................................. - 127 - 9.4.1 external signals ...................................................................................................- 128 - 9.4.2 registers...............................................................................................................- 128 - 9.4.3 operation .............................................................................................................- 136 - 9.4.4 a/d converter......................................................................................................- 142 - 9.5 uart/sir............................................................................................................... - 145 - 9.5.1 external signals ...................................................................................................- 146 - 9.5.2 registers...............................................................................................................- 147 - 9.5.3 fifo interrupt mode operation..........................................................................- 158 - 9.5.4 fifo polling mode operation ............................................................................- 159 - 9.6 smart c ard i nterface ....................................................................................... - 161 -
contents magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) iii 9.6.1 external signals ...................................................................................................- 162 - 9.6.2 registers...............................................................................................................- 163 - 9.6.3 smart card interface operat ion flow char t .......................................................- 177 - 9.7 s ynchronous s erial i nterface (ssi) .................................................................. - 179 - 9.7.1 register description .............................................................................................- 180 - 9.7.2 overview ..............................................................................................................- 189 - 9.7.3 operational description ......................................................................................- 190 - 9.7.4 ssi ac timming ...................................................................................................- 193 - 9.8 smc c ontroller .................................................................................................. - 195 - 9.8.1 external signals ...................................................................................................- 196 - 9.8.2 registers...............................................................................................................- 196 - 9.8.3 smc access using ebi interface ..........................................................................- 207 - 9.9 timer & pwm...................................................................................................... - 209 - 9.9.1 external signals ...................................................................................................- 210 - 9.9.2 registers...............................................................................................................- 210 - 9.9.3 operation .............................................................................................................- 217 - 9.10 w atchdog t imer .................................................................................................. - 235 - 9.10.1 registers.............................................................................................................- 236 - 9.10.2 watchdog timer oper ation ................................................................................- 238 - 9.11 rtc ....................................................................................................................... - 243 - 9.11.1 external signals .................................................................................................- 244 - 9.11.2 registers.............................................................................................................- 245 - 9.11.3 operation ...........................................................................................................- 255 - 9.12 2-w ire s erial b us i nterface ............................................................................. - 259 - 9.12.1 external signals .................................................................................................- 260 - 9.12.2 registers.............................................................................................................- 260 - 9.12.3 operation ...........................................................................................................- 265 - 9.13 m at r i x k eyboard i nterface c ontroller ........................................................ - 275 - 9.13.1 external signals .................................................................................................- 276 - 9.13.2 registers.............................................................................................................- 276 - 9.13.3 operation ...........................................................................................................- 281 - 9.14 gpio ..................................................................................................................... - 289 - 9.14.1 external signals .................................................................................................- 290 - 9.14.2 registers.............................................................................................................- 292 - 9.14.3 operations..........................................................................................................- 309 - 9.14.4 gpio rise and fall time ...................................................................................- 314 - 10 debug and test inter face .......................................................................- 315 - 10.1 o verview .............................................................................................................. - 315 - 10.2 s oftware d evelopment d ebug and t est i nterface ........................................ - 315 - 10.3 t est a ccess p ort and b oundary -s can ............................................................. - 316 - 10.3.1 reset...................................................................................................................- 317 - 10.3.2 pull-up register .................................................................................................- 318 - 10.3.3 instruction register............................................................................................- 318 - 10.3.4 public instructions .............................................................................................- 319 - 10.3.5 test data register ..............................................................................................- 323 - 10.3.6 boundary scan interf ace signals .......................................................................- 325 - 11 electrical char acteristi cs .........................................................................i 11.1 a bsolute m aximum r at i n g s ....................................................................................... i 11.2 dc characteristics .................................................................................................... ii 11.3 a/d c onverter e lectrical c haracteristics .......................................................... iii 12 appendix......................................................................................................................i
contents magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) iv list of figures figure 2-1. 208 pin diagram.................................................................................................... ...... - 13 - figure 2-2. 208 lqfp dimensions-1............................................................................................. - 15 - figure 2-3. 208 lqfp dimensions-2 < detail ?a? (scale 1/30) > ....................................... - 16 - figure 2-4. 208 cabga top and side view................................................................................... - 16 - figure 2-5. 208 cabga bottom view ............................................................................................ - 17 - figure 4-1. internal boot rom / external static memory map (romswap=0) ............................ - 28 - figure 4-2. internal boot rom / external static memory map (romswap=1) ............................ - 29 - figure 4-3. internal sram / external sdram memory map......................................................... - 30 - figure 4-4. peripherals address map ............................................................................................ - 32 - figure 5-1. software boot flows ................................................................................................ ... - 34 - figure 6-1. pmu block diagram.................................................................................................. .. - 37 - figure 6-2. fclk frequency update when the bit 6 is set ........................................................... - 49 - figure 6-3. fclk / bclk relation............................................................................................... ... - 49 - figure 6-4. pmu power management state diagram ................................................................... - 51 - figure 6-5. a cold reset event ................................................................................................. .... - 54 - figure 6-6. npor / nreset / softwarereset function ................................................................ - 55 - figure 6-7. software generated warm reset ............................................................................... - 56 - figure 6-8. an externally ge nerated warm reset ........................................................................ - 57 - figure 7-1. sdram controller block diagram .............................................................................. - 59 - figure 7-2. sdram controller software ex ample and memory operation diagram..................... - 63 - figure 7-3. 256mbitx16 (4banks) device connection ................................................................... - 67 - figure 7-4. 128mbitx16 (4banks) device connection ................................................................... - 67 - figure 7-5. 64mbitx16 (4banks) device connection ..................................................................... - 67 - figure 7-6. 16mbitx16 (2banks) device connection ..................................................................... - 68 - figure 7-7. writ e miss flusing................................................................................................. ...... - 70 - figure 7-8. read hit flusing ................................................................................................... ...... - 70 - figure 7-9. timer timeover flusing............................................................................................. ... - 71 - figure 8-1. data flow at 16-bit width memory................................................................................ - 7 8 - figure 8-2. data flow at 8-bit width memory.................................................................................. - 78 - figure 8-3. 16-bit bank configuratio n with 8-bit width memory ...................................................... - 79 - figure 8-4. 8-bit bank configuratio n with 8-bit width memory ........................................................ - 79 - figure 8-5. 16-bit bank configuratio n with 16-bit width memory .................................................... - 79 - figure 9-1. block digram of lcd controller ................................................................................... - 85 - figure 9-2. pixel display sequence of ld bus ............................................................................... - 97 - figure 9-3. changing polarity of lcd panel signals ...................................................................... - 98 - figure 9-4. block diagram of cl ock source gener ation................................................................... - 99 - figure 9-5. timing diagram of a line with llp, lcp, and ld signals............................................ - 100 - figure 9-6. timing diagram of lfp signal.................................................................................... - 1 01 - figure 9-7. timing diagram of a fram e be different by the differ .................................................. - 102 - figure 9-8. pixel display order for big and little-endian pixel alignment in 2-bpp mode ........... - 104 - figure 9-9. usb block diagram .................................................................................................. .- 114 - figure 9-10. usb serial interface engine ................................................................................... - 12 2 - figure 9-11. block diagram of adc, adc i/f............................................................................... - 127 - figure 9-12. adc clock & da ta sampling cl ock .......................................................................... - 136 - figure 9-13. adc operat ing stop condi tion.................................................................................. - 13 6 - figure 9-14. data loading timing ............................................................................................... .. - 137 - figure 9-15. data sampling sequence ? trate is 2?b11 / sshot is 1?b0 / swinvt is 1?b0...... - 138 - figure 9-16. data sampling sequence ? trate is 2?b11 / sshot is 1?b1 / swinvt is 1?b0...... - 139 - figure 9-17. data sampling sequence ? trate is 2?b10 / sshot is 1?b0 / swinvt is 1?b1 ..... - 139 - figure 9-18. interrupt generating timing ? trate is 2?b11 / sshot is 1?b0 ............................... - 140 - figure 9-19. interrupt generating timing ? trate is 2?b11 / sshot is 1?b1 ............................... - 140 - figure 9-20. adc direct access mode......................................................................................... - 1 41 - figure 9-21. block diagram of a/d converter.............................................................................. - 142 -
contents magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) v figure 9-22. timing diagram of a/d converter ............................................................................ - 144 - figure 9-23. ssi block diagram................................................................................................. . - 179 - figure 9-24. transfer format (single transfer) ........................................................................... - 191 - figure 9-25. transfer format (b ack to back transfer) ................................................................ - 192 - figure 9-26. smc access using the ebi interface....................................................................... - 207 - figure 9-27. block diagram of timer/pwm............................................................................... - 209 - figure 9-28. clock select logic ................................................................................................ .... - 217 - figure 9-29. non-repeat mode operation .................................................................................... - 219 - figure 9-30. repeat mode operation .......................................................................................... - 2 20 - figure 9-31. byte counter operat ion in non-repeat mode ............................................................ - 221 - figure 9-32. byte counter oper ation in repea t mode ................................................................... - 222 - figure 9-33. clock source of t3 count is t2match event....................................................... - 223 - figure 9-34. software is sued reset co mmand............................................................................. - 224 - figure 9-35. output and interrupt generation in repeat mode ..................................................... - 225 - figure 9-36. output and interrupt generation in non-r epeat mode .............................................. - 226 - figure 9-37. clock select logic ................................................................................................ .... - 227 - figure 9-38. timing diagram of pwm channel when outputinvert = 0 ................................ - 228 - figure 9-39. timing diagram of pwm channel when outputinvert = 1 ................................ - 229 - figure 9-40. pwm waveform when outputinvet = 0, duty = 30% ......................................... - 230 - figure 9-41. pwm waveform when outputinvet = 0, duty = 80% ......................................... - 230 - figure 9-42. pwm waveform when outputinvet = 1, duty = 30% ......................................... - 232 - figure 9-43. pwm waveform when outputinvet = 1, duty = 80% ......................................... - 232 - figure 9-44. software is sued reset co mmand............................................................................. - 233 - figure 9-45. rtc block diagram ................................................................................................ - 243 - figure 9-46. block diagram of 2-wire sbi ................................................................................... - 25 9 - figure 9-47. connection of devices to the 2-wire serial bus ....................................................... - 265 - figure 9-48. data validity ..................................................................................................... ....... - 266 - figure 9-49. start and stop conditions .................................................................................. - 266 - figure 9-50. scl synchronization between multiple masters...................................................... - 267 - figure 9-51. arbitration between two masters ............................................................................. - 268 - figure 9-52. address and data packet of 2-wire sbi .................................................................. - 269 - figure 9-53. ack signal generation ............................................................................................ - 270 - figure 9-54. waveform when 2-wire sbi is master tran smitter................................................... - 271 - figure 9-55. waveform when 2-wire sbi is master receiver....................................................... - 272 - figure 9-56. waveform when 2-wire sbi is slave tran smitter ..................................................... - 273 - figure 9-57. waveform when 2-wire sbi is slave receiver ......................................................... - 274 - figure 9-58. block diagram of keyboard cont roller...................................................................... - 275 - figure 9-59. keyboard matr ix configuration ................................................................................ - 281 - figure 9-60. kscano output timing ........................................................................................... - 2 82 - figure 9-61. clock divider of keyboard cont roller ........................................................................ - 283 - figure 9-62. key scan period and column per iod........................................................................ - 283 - figure 9-63. wakeup interrupt & key scanning enabled ............................................................. - 284 - figure 9-64. a flow chart of se tting keyboard controller............................................................... - 285 - figure 9-65. kbvr0/1 write timing .............................................................................................. - 286 - figure 9-66. kscano[3:2] are configured for gpio................................................................... - 288 - figure 9-67. block diagram of gpio ........................................................................................... - 289 - figure 9-68. alternate port functions .......................................................................................... . - 310 - figure 9-69. interrupt request................................................................................................. ......- 311 - figure 9-70. de-bouncing of port a ............................................................................................. - 313 - figure 9-71. pad organization .................................................................................................. ... - 314 - figure 9-72. timing diagram of bi-dir ectional pad (cmos or ttl).............................................. - 314 - figure 10-1. test access port(tap) controller state transitions................................................. - 316 - figure 10-2. boundary scan block diagram ............................................................................... - 323 - figure 10-3. boundary scan general timing .............................................................................. - 325 - figure 10-4. boundary scan tri-state timing .............................................................................. - 325 -
contents magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) vi figure 10-5. boundary scan reset timing.................................................................................. - 326 -
contents magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) vii list of tables table 2-1 pin signal type definition........................................................................................... ... - 18 - table 2-2 external signal functions ............................................................................................ .. - 20 - table 4-1 top-leve l address map................................................................................................ ... - 27 - table 4-2 peripherals base addresses.......................................................................................... - 31 - table 5-1. pin configuration ................................................................................................... ....... - 33 - table 5-2. na nd / mmc map ...................................................................................................... .. - 34 - table 6-1. pmu register summary............................................................................................... - 38 - table 6-2. bit settings for a cold reset event within pmursr register .................................... - 54 - table 6-3. bit settings for a software generated warm reset within reset / status register ........ - 56 - table 6-4. bit settings for a warm reset within reset / status register ........................................ - 57 - table 7-1 sdram controller register summary .......................................................................... - 61 - table 7-2 sdram row/column address map .............................................................................. - 66 - table 7-3 sdram device selection .............................................................................................. - 66 - table 8-1 static memory controller register summary................................................................. - 74 - table 8-2. timing values for read access in single mode data transfer (bclk=33mhz) ............... - 80 - table 8-3. timing values for read access in burst mode data transfer (bclk=33mhz) ................ - 81 - table 8-4. timing values for write access (bclk=33mhz)............................................................ - 82 - table 9-1. lcd controller register summary ............................................................................... - 86 - table 9-2. lcd color/grayscale inte nsities and modulat ion rates............................................... - 95 - table 9-3. interrupt contro ller register summary ....................................................................... - 108 - table 9-4 usb slave interface register summary.......................................................................- 115 - table 9-5. usb supported pid types ......................................................................................... - 12 3 - table 9-6 usb supported setup requests ................................................................................. - 124 - table 9-7. adc controller register summary ............................................................................. - 128 - table 9-8 uart/sir regi ster summary ..................................................................................... - 147 - table 9-9 baud rate with decimal divi sor at 3.92308mhz cl ock input ...................................... - 153 - table 9-10 smart card interface register summary................................................................... - 163 - table 9-11 baud rate with decimal divi sor at 3.55556mhz clock input..................................... - 169 - table 9-12 smartmedia controller register summary ................................................................ - 196 - table 9-13. timer register summary.......................................................................................... - 2 10 - table 9-14. watchdog timer register summary ......................................................................... - 236 - table 9-15 non-amba signals within rtc core block ............................................................... - 244 - table 9-16. 2-wire sbi?s register summary ............................................................................... - 260 - table 9-17. matrix keyboard interface controller register summary.......................................... - 276 - table 9-18. scan rate calculation from clksel ......................................................................... - 284 - table 9-19. estimated t intr according to clksel....................................................................... - 286 - table 9-20. possible configuration of kscano pins when keyboard matrix is connected.......... - 287 - table 9-21. possible configuration of kscani pins when keyboard matrix is connected............ - 288 - table 9-22. interrupt sources of i/os (to interrupt controller unit) ................................................ - 312 - table 9-23. propagation delays (n s) for sample pad loads.......................................................... - 314 - table 11-1. maximum ratings .................................................................................................... ........... i table 11-2. operating range .................................................................................................... ............ i table 11-3. cmos signal pin characteristics .................................................................................... .... ii table 11-4. ttl signal pin characte ristics..................................................................................... ........ ii table 11-5. a/d conver ter characte ristics ...................................................................................... ...... iii
contents magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) viii
architectural overview magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 9 - 1 architectural overview 1.1 processor the arm720t core incorporates an 8kb unified write-through cache, and an 8 data entry, 4-address entry write buffer. it also incorporates an mmu with a 64 entry tlb. 1.2 video the integrated lcd controller can control color and monochrome stn displays, up to 640x480 (vga) resolution. 1, 2, 4, and 8 bit-per-pixel is supported and a patented gray scaler can directly generate 16 gray scales. 1.3 memory the 16-bit external data path interfaces to rom or flash devices. burst mode roms are supported, for increased performanc e, allowing operating system code to be executed directly from rom. 1.4 internal bus structure the HMS30C7210 internal bus organization is based upon the amba standard, but with some minor modifications to the peripheral buses (the apbs). there are two main buses in the HMS30C7210: ? the main system bus (the asb) to which the cpu and memory controllers are connected ? the apb to peripherals are connected 1.4.1 asb the asb is designed to allow the arm continuous access to both, the rom and the sdram interface. the sdram controller straddles both the asb and the video dma bus so the lcd can access the sdram controller simultaneously with activity on the asb. this means that the arm can read code from rom, or access a peripheral, without being interrupted by video dma. the HMS30C7210 uses a modified arbiter to control mastership on the main asb bus. the arbiter only arbitrates on quad-word boundaries, or when the bus is idle. this is to get the best performance with the arm720t, which uses a quad-word cache line, and also to get the best performance from the sdram, which uses a burst size of eight half-words per access. by arbitratin g only when the bus is idle or on quad-word boundaries (a[3:2] = 11), it ensures that cache line fills are not broken up, hence sdram bursts are not broken up. the sdram controller controls video asb arbitration. this is explained in 6.5 arbitration. 1.4.2 video bus the video bus connects the lcd controller with the internal sram and the sdram controller. data transfers are dma controlled. the video bus consists of an address bus, data bus and control signals to/from the internal sram and the sdram controller. the lcd registers are programmed through the fast apb. the sdram
architectural overview magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 10 - controller arbitrates between asb, video access requests. video always has higher priority than asb access requests. the splitting asb/video bus allows slow asb device accesses internal sram and sdram without blocking video dma. 1.4.3 apb the most apb peripherals do not support dma transfers. this arrangement of running most of the peripherals at a slower clock, and reducing the load on the faster bus, results in significantly reduced power consumption. the apb bus connects to the main asb bus via bridges. the apb bridge takes care of all resynchronization, handing over data and control signals between the asb and uart clock domains in a safe and reliable manner. usb, lcd controller, smc and spi are operated at the speed of the asb. theses are high performance peripherals. 1.5 sdram controller the sdram controller is a key part of the HMS30C7210 architecture. the sdram controller has two data ports - one for video dma and one for the main asb - and interfaces to 16-bit wide sdrams. one to four 16, 64, 128, or 256 mbits x 16-bit devices are supported, giving a memory size ranging from 2 to 64 mbytes. the main asb and video dma buses are independent, and operate concurrently. the video bus has always higher priority than the main bus. the video interface consists of address, data and control signals. the video access burst size is fixed to 16 words. the address is non-incrementing for words within a burst (as the sdram controller only makes use of the first address for each burst request). 1.6 peripherals universal serial bus (usb) device controller the usb device controller is used to transfer data from/to host system like pc in full- speed (12mbits/s) mode. no external usb transceiver is necessary. universal asynchronous receiver and transmitter (uart) six uart ports are implemented. uart0,1 supports smart card interface signals. irda / modem irda uses uart4 for its sir transfer in 115 kbit/s speed. uart5 supports full modem interface signals. pulse-width-modulated (pwm) interface two pwm output signals are generated. the pins are used as gpio when not used for pwm. matrix keyboard interface matrix keyboard interface supports 6x6. the pins are used as gpio when not used for matrix keyboards.
architectural overview magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 11 - adc 3 channel adc is implemented for touch panel, monitoring of battery voltage or general purpose. pll cpu, video and usb clocks are generated by two plls with 6 mhz input clock. 1.7 power management the HMS30C7210 incorporates advanced power management functions, allowing the whole device to be put into a standby mode, when only the real time clock runs. the sdram is put into low-power self-refresh mode to preserve its contents. the HMS30C7210 may be forced out of this stat e by either a real-time clock wake-up interrupt, a user wake-up event (which would generally be a user pressing the ?on? key) or by the uart ring-indicate input. the power management unit (pmu) controls the safe exit from standby mode to operational mode, ensuring that sdram contents are preserved. in addition, halt and slow modes allow the processor to be halted or run at reduced speed to reduce power consumption. the processor can be quickly brought out of the halted state by a peripheral interrupt. the advanced power management unit controls all this functionality. in addition, individual devices and peripherals may be powered down when they are not in use. the HMS30C7210 is designed for battery-powered portable applications and incorporates innovative design features in the bus structure and the pmu to reduce power consumption. the apb bus allows peripherals to be clocked slowly hence reducing power consumption. the use of two buses reduces the number of nodes that are toggled during a data access, and thereby further reducing power consumption. in addition, clocks to peripherals that are not active can also be gated. 1.7.1 clock gating the high performance peripherals, such as the sdram controller and the lcd controller, run most of the time at high frequencies and careful design, including the use of clock gating, has minimized their power consumption. any peripherals can be powered down completely when not in use. 1.7.2 pmu the power management unit (pmu) is used to control the overall state the system is in. the system can be in one of five states: run the system is running normally. all clocks are running (except where gated locally). the sdram controller is performing normal refresh. slow the cpu is switched into fastbus mode, and hence runs at the bclk rate (half the fclk rate). this is the default mode after exiting deep sleep mode or system power on.
architectural overview magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 12 - idle in this mode, the pmu becomes the bus master until there is either a fast or normal interrupt for the cpu. this will cause the clocks in the cpu to stop when it attempts an asb access. the HMS30C7210 can enter this mode by writing 0x2 to the bits [2:0] of the pmumr when in run or slow mode, or by wakeup signal activation while in sleep or deep sleep mode. sleep in this mode, the sdram is put into self-refresh mode, and internal clocks are gated off. this mode can only be entered from idle mode (the pmu bus master must have the mastership of the asb before this mode can be entered). the pmu must be the bus master to ensure that the system is sto pped in a safe state, and is not half way through a sdram write (for example). both the video and communication clocks (vclk and cclk) should be disabled before entering this state. usually the cpu would only drop in at this mode on the way to the deep sleep mode. deep sleep in the deep sleep mode, the crystal oscillator for the 6-mhz pll input clock and the plls are disabled. this is the lowest power state available. only the 32-khz rtc oscillator runs and provides clocks for the rtc logic and the debouncing logic of the pmu, which runs at the 4-khz frequency (i.e. the rtc clock frequency divided by 8). everything else is powered down, and sdram is in self refresh mode. this is the normal system "off" mode. the HMS30C7210 can get out of the sleep and deep sleep modes either by a user wake-up event (generally pressing the "on" key), by an rtc wake-up alarm, or by a modem ring indicate event. these wake-up sources go directly to the pmu. 1.8 test and debug the HMS30C7210 incorporates the arm standard test interface controller (tic) allowing 32-bit parallel test vectors to be passed onto the internal bus. this allows access to the arm720t macro-cell core, and also to memory mapped devices and peripherals within the HMS30C7210. in addition, the arm720t includes support for the arm debug architecture (embedded ice), which makes use of a jtag boundary scan port to support debug of code on the embedded processor. the same boundary scan port is also used to support a normal pad-ring boundary scan for board level test applications.
signal description magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 13 - 2 signal description 2.1 208-pin diagram HMS30C7210 top view kscani[0] kscani[1] kscani[2] kscani[3] kscani[4] kscani[5] vss vdd kscano[0] kscano[1] kscano[2] kscano[3] kscano[4] kscano[5] tdi tck tms ntrst tdo oscin oscout rtcvdd rtcoscin rtcoscout usbn usbp usbvss usbvdd pllvss48m pllvdd48m pllvss60m pllvdd60m vsscore vddcore adcvdd adcavref adin[0] adin[1] adin[2] adcvss npmwakeup npor nreset pmbatok npllenable ntest scrst[0] scio[0] vss vdd scclk[0] scpres[0] scrst[1] scio[1] scclk[1] scpres[1] uart2rx uart2tx uart3rx uart3tx irda4rx irda4tx gpiob14 gpiob15 touchxp vss vdd touchyp touchxn touchyn nuring nudcd nudsr nucts nurts nudtr uart5rx uart5tx nsmcd vsscore vddcore nsmrb smale smcle nsmce nsmre vss vdd nsmwe nsmwp smd[0] smd[1] smd[2] smd[3] smd[4] smd[5] smd[6] smd[7] romswap bootsel nrcs[0] nrcs[1] nrcs[2] nrcs[3] vss vdd nroe nrwe[0] nrwe[1] rd[0] rd[1] rd[2] rd[3] rd[4] rd[5] rd[6] rd[7] rd[8] vss vdd rd[9] rd[10] rd[11] rd[12] rd[13] rd[14] rd[15] ra[0] ra[1] ra[2] ra[3] vsscore vddcore vss vdd ra[4] ra[5] ra[6] ra[7] ra[8] ra[9] sa10 ra[10] ra[11] ra[12] vss vdd ra[13] ra[14] ra[15] ra[16] ra[17] ra[18] ra[19] ra[20] ra[21] ra[22] ra[23] vss vdd dqml dqmu nswe ncas nras nscs[0] nscs[1] scke[0] scke[1] vss sclk vdd llp lac lblen lcp lfp lcden ld[0] ld[1] ld[2] ld[3] ld[4] vsscore vddcore ld[5] ld[6] ld[7] spirx[0] vss vdd spitx[0] nspics[0] spiclk[0] spirx[1] spitx[1] nspics[1] spiclk[1] 2wsiclk 2wsidat timer[0] timer[1] timer[2] timer[3] pwm[0] pwm[1] testscan scanen ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 HMS30C7210 top view kscani[0] kscani[1] kscani[2] kscani[3] kscani[4] kscani[5] vss vdd kscano[0] kscano[1] kscano[2] kscano[3] kscano[4] kscano[5] tdi tck tms ntrst tdo oscin oscout rtcvdd rtcoscin rtcoscout usbn usbp usbvss usbvdd pllvss48m pllvdd48m pllvss60m pllvdd60m vsscore vddcore adcvdd adcavref adin[0] adin[1] adin[2] adcvss npmwakeup npor nreset pmbatok npllenable ntest scrst[0] scio[0] vss vdd scclk[0] scpres[0] scrst[1] scio[1] scclk[1] scpres[1] uart2rx uart2tx uart3rx uart3tx irda4rx irda4tx gpiob14 gpiob15 touchxp vss vdd touchyp touchxn touchyn nuring nudcd nudsr nucts nurts nudtr uart5rx uart5tx nsmcd vsscore vddcore nsmrb smale smcle nsmce nsmre vss vdd nsmwe nsmwp smd[0] smd[1] smd[2] smd[3] smd[4] smd[5] smd[6] smd[7] romswap bootsel nrcs[0] nrcs[1] nrcs[2] nrcs[3] vss vdd nroe nrwe[0] nrwe[1] rd[0] rd[1] rd[2] rd[3] rd[4] rd[5] rd[6] rd[7] rd[8] vss vdd rd[9] rd[10] rd[11] rd[12] rd[13] rd[14] rd[15] ra[0] ra[1] ra[2] ra[3] vsscore vddcore vss vdd ra[4] ra[5] ra[6] ra[7] ra[8] ra[9] sa10 ra[10] ra[11] ra[12] vss vdd ra[13] ra[14] ra[15] ra[16] ra[17] ra[18] ra[19] ra[20] ra[21] ra[22] ra[23] vss vdd dqml dqmu nswe ncas nras nscs[0] nscs[1] scke[0] scke[1] vss sclk vdd llp lac lblen lcp lfp lcden ld[0] ld[1] ld[2] ld[3] ld[4] vsscore vddcore ld[5] ld[6] ld[7] spirx[0] vss vdd spitx[0] nspics[0] spiclk[0] spirx[1] spitx[1] nspics[1] spiclk[1] 2wsiclk 2wsidat timer[0] timer[1] timer[2] timer[3] pwm[0] pwm[1] testscan scanen ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- ----- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 figure 2-1. 208 pin diagram
signal description magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 14 - 2.2 208 pin / ball name pin no. ball no. pad name pin no. ball no. pad name pin no. ball no. pad name pin no. ball no. pad name 1 a1 kscani[0] 53 u1 scrst[1] 105 u17 vss 157 a17 ra[22] 2 b2 kscani[1] 54 t2 scio[1] 106 t16 vdd 158 b16 ra[23] 3 b1 kscani[2] 55 u2 scclk[1] 107 t17 nroe 159 a16 vss 4 c1 kscani[3] 56 u3 scpres[1] 108 r17 nrwe[0] 160 a15 vdd 5 d3 kscani[4] 57 r4 uart2rx 109 p15 nrwe[1] 161 c14 dqml 6 c2 kscani[5] 58 t3 uart2tx 110 r16 rd[0] 162 b15 dqmu 7 d1 vss 59 u4 uart3rx 111 p17 rd[1] 163 a14 nswe 8 e4 vdd 60 p5 uart3tx 112 n14 rd[2] 164 d13 ncas 9 e3 kscano[0] 61 r5 irda4rx 113 n15 rd[3] 165 c13 nras 10 d2 kscano[1] 62 t4 irda4tx 114 p16 rd[4] 166 b14 nscs[0] 11 e2 kscano[2] 63 t5 gpiob14 115 n16 rd[5] 167 b13 nscs[1] 12 f3 kscano[3] 64 r6 gpiob15 116 m15 rd[6] 168 c12 scke[0] 13 f4 kscano[4] 65 p6 touchxp 117 m14 rd[7] 169 d12 scke[1] 14 e1 kscano[5] 66 u5 vss 118 n17 rd[8] 170 a13 vss 15 f2 tdi 67 t6 vdd 119 m16 vss 171 b12 sclk 16 g3 tck 68 r7 touchyp 120 l15 vdd 172 c11 vdd 17 g4 tms 69 p7 touchxn 121 l14 rd[9] 173 d11 llp 18 f1 ntrst 70 u6 touchyn 122 m17 rd[10] 174 a12 lac 19 g2 tdo 71 t7 nuring 123 l16 rd[11] 175 b11 lblen 20 h3 oscin 72 r8 nudcd 124 k15 rd[12] 176 c10 lcp 21 h4 oscout 73 p8 nudsr 125 k14 rd[13] 177 d10 lfp 22 g1 rtcvdd 74 u7 nucts 126 l17 rd[14] 178 a11 lcden 23 h2 rtcoscin 75 t8 nurts 127 k16 rd[15] 179 b10 ld[0] 24 j3 rtcoscout 76 r9 nudtr 128 j15 ra[0] 180 c9 ld[1] 25 j4 usbn 77 p9 uart5rx 129 j14 ra[1] 181 d9 ld[2] 26 h1 usbp 78 u8 uart5tx 130 k17 ra[2] 182 a10 ld[3] 27 j2 usbvss 79 t9 nsmcd 131 j16 ra[3] 183 b9 ld[4] 28 k3 usbvdd 80 r10 vsscore 132 h15 vsscore 184 c8 vsscore 29 k4 pllvss48m 81 p10 vddcore 133 h14 vddcore 185 d8 vddcore 30 j1 pllvdd48m 82 u9 nsmrb 134 j17 vss 186 a9 ld[5] 31 k2 pllvss60m 83 t10 smale 135 h16 vdd 187 b8 ld[6] 32 l3 pllvdd60m 84 r11 smcle 136 g15 ra[4] 188 c7 ld[7] 33 l4 vsscore 85 p11 nsmce 137 g14 ra[5] 189 d7 spirx[0] 34 k1 vddcore 86 u10 nsmre 138 h17 ra[6] 190 a8 vss 35 l2 adcvdd 87 t11 vss 139 g16 ra[7] 191 b7 vdd 36 m3 adcvref 88 r12 vdd 140 f15 ra[8] 192 c6 spitx[0] 37 m4 adin[0] 89 p12 nsmwe 141 f14 ra[9] 193 d6 nspics[0] 38 l1 adin[1] 90 u11 nsmwp 142 g17 sa10 194 a7 spiclk[0] 39 m2 adin[2] 91 t12 smd[0] 143 f16 ra[10] 195 b6 spirx[1] 40 n3 adcvss 92 r13 smd[1] 144 e15 ra[11] 196 c5 spitx[1] 41 n4 npmwakeup 93 p13 smd[2] 145 e14 ra[12] 197 d5 nspics[1] 42 m1 npor 94 u12 smd[3] 146 f17 vss 198 a6 spiclk[1] 43 n2 nreset 95 t13 smd[4] 147 e16 vdd 199 b5 2wsiclk 44 p3 pmbatok 96 r14 smd[5] 148 d15 ra[13] 200 c4 2wsidat 45 p4 npllenable 97 p14 smd[6] 149 d14 ra[14] 201 d4 timer[0] 46 n1 ntest 98 u13 smd[7] 150 e17 ra[15] 202 a5 timer[1] 47 r3 scrst[0] 99 r15 romswap 151 c15 ra[16] 203 c3 timer[2] 48 p2 scio[0] 100 t14 bootsel 152 d16 ra[17] 204 b4 timer[3] 49 p1 vss 101 u14 nrcs[0] 153 d17 ra[18] 205 a4 pwm[0] 50 r1 vdd 102 u15 nrcs[1] 154 c17 ra[19] 206 a3 pwm[1] 51 r2 scclk[0] 103 t15 nrcs[2] 155 c16 ra[20] 207 b3 testscan 52 t1 scpres[0] 104 u16 nrcs[3] 156 b17 ra[21] 208 a2 scanen
signal description magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 15 - 2.2.1 lqfp type dimensions - all dimensions in mm . figure 2-2. 208 lqfp dimensions-1
signal description magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 16 - figure 2-3. 208 lqfp dimensions-2 < detail ?a? (scale 1/30) > 2.2.2 cabga type dimensions figure 2-4. 208 cabga top and side view
signal description magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 17 - figure 2-5. 208 cabga bottom view
signal description magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 18 - 2.3 pin descriptions table 2-2 describes the function of all the external signals to the HMS30C7210. type description type description o output ao analog output i input ai analog input io input/output aio analog input/output is input with schmitt level input threshold p power input u suffix to indicate integral pull-up d suffix to indicate integral pull-down table 2-1 pin signal type definition 2.3.1 external signal functions function signal name signal type lqfp pin number description ld[7:0] o 179~183 186~188 lcd data bus ld[3:0] for 4bit bus lcd and ld[7:0] for 8-bit bus lcd lcp o 176 lcd clock pulse llp o 173 lcd line pulse lfp o 177 lcd frame pulse lac o 174 lcd ac bias lcden o 178 display enable signal for lcd enables high voltage to lcd lcd lblen o 175 lcd backlight enable ra[24:0] o 128~131 136~141 143~145 148~158 rom address bus rd[15:0] io 110~118 121~127 rom data bus nrcs[3:0] o 101~104 rom chip select outputs nroe o 107 rom output enable signal smi (static memory interface) nrwe[1:0] o 108~109 rom write enable signals ra[14:11],[9:0] o 128~131 136~141 144~145 148~149 sdram address bus sa10 o 142 sdram address bus (for precharge command) rd[15:0] io 110~118 121~127 sdram data bus sclk o 171 sdram clock output scke[1:0] o 168~169 sdram clock enable outputs nras o 165 sdram row address select output ncas o 164 sdram column address select output nswe o 163 sdram write enable output nscs[1:0] o 166~167 sdram chip select outputs dqml o 161 sdram lower data byte enable sdram interface dqmu o 162 sdram upper data byte enable scio[1:0] io 48,54 smartcard data i/o (uart 0,1 tx) scrst[1:0] io 47,53 smartcard reset outputs (uart 0,1 rx) scpres[1:0] i 52,56 smartcard presence detection (not used at uart mode) smart card interface (uart 0,1) scclk[1:0] o 51,55 smartcard clock outputs (not used at uart mode) uart2tx o 58 uart2 serial data output uart 2 uart2rx i 57 uart2 serial data input
signal description magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 19 - function signal name signal type lqfp pin number description uart3tx o 60 uart3 serial data output uart 3 uart3rx i 59 uart3 serial data input irda4tx o 62 irda serial data output (uart4 tx) irda (uart 4) irda4rx i 61 irda serial data input (uart4 rx) uart5tx o 78 uart5 serial data output uart5rx i 77 uart5 serial data input nudcd i 72 uart5 data carrier detect input nudsr i 73 uart5 data set ready input nucts i 74 uart5 clear to send input nudtr o 76 uart5 data terminal ready nurts o 75 uart5 request to send uart 5 (for a modem device application) nuring i 71 uart5 ring input signal spitx[1:0] o 192,196 spi data output spirx[1:0] i 189,195 spi data input nspics[1:0] o 193,197 spi chip select signal ssi (spi) spiclk[1:0] o 194,198 spi clock output 2wsiclk io 199 2wsi clock input/output 2wsi 2wsidat io 200 2wsi data input/output usbp aio 26 usb positive signal usbn aio 25 usb negative signal usbvdd p 28 usb analog vdd usb usbvss p 27 usb analog vss timer[3:0] o 201~204 timer data output timer, pwm pwm[1:0] o 205~206 pulse width modulator data output kscano[5:0] o 9~14 matrix keyboard scan output matrix keyboard kscani[5:0] i 1~6 matrix keyboard scan input smd[7:0] io 91~98 smc bi-directional data signal nsmwp o 90 smc write protect nsmwe o 89 smc write enable smale o 83 smc address latch enable smcle o 84 smc command latch enable nsmcd i 79 smc card detection signal nsmce o 85 smc chip enable nsmre o 86 smc read enable smc (smartmedia card) nsmrb i 82 smc ready/busy signal touchxp io 65 touch screen switch x-positive drive touchxn o 69 touch screen switch x-negative drive touchyp io 68 touch screen switch y-positive drive touchyn o 70 touch screen switch y-negative drive adin[2:0] ai 37~39 adc input for battery, touch rtcvdd i 22 rtc vdd adcvdd p 35 adc analog vdd adcvss p 40 adc analog vss adc adcvref ai 36 adc reference voltage pllvdd48m p 30 pll 48mhz analog vdd pllvss48m p 29 pll 48mhz analog vss pllvdd60m p 32 pll 60mhz analog vdd pll pllvss60m p 31 pll 60mhz analog vss gpioa[11:0] io 1~6,9~14 general purpose input/output signals gpiob[27:0] io 47,48,51~65,68 ~78 general purpose input/output signals gpio gpioc[15:0] io 79,82~86, 89~98 general purpose input/output signals
signal description magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 20 - function signal name signal type lqfp pin number description gpiod[24:0] io 103,104,161~16 9,173~183,186~ 188 general purpose input/output signals gpioe[15:0] io 189,192~206 general purpose input/output signals romswap i 99 swap internal rom area / external flash rom area boot bootsel i 100 select boot bus width and direction (smc/mmc) npor is 42 power on reset input. schmitt level input with pull-up npmwakeup is 41 wake-up ?on-key? input. nreset io 43 reset input system pmbatok i 44 main battery ok rtcoscin i 23 rtc oscillator input rtcoscout o 24 rtc oscillator output oscin i 20 main oscillator input oscillator oscout o 21 main oscillator output vddcore p 34,81,133, 185 core vdd supply (3.3v) vsscore p 33,80,132,184 core vss supply vdd p 8,50,67,88 106,120,135,14 7,160,172, 191 io vdd supply (3.3v) digital power / ground vss p 7,49,66,87 105,119,134,14 6,159,170, 190 io vss supply tck iu 16 jtag boundary scan and debug test clock ntrst id 18 jtag boundary scan and debug test reset tms iu 17 jtag boundary scan and debug test mode select tdi iu 15 jtag boundary scan and debug test data input jtag tdo o 19 jtag boundary scan and debug test data output npllenable i 45 pll enable input testscan id 207 scan test mode enable scanen id 208 scan chain pass enable test ntest iu 46 test mode select input table 2-2 external signal functions
signal description magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 21 - 2.3.2 pin specific description key to pad types : o (output), i (input), io (input / output), a (analog), c (cryst al oscillator), od (o utput open drain), s (input schmitt level ), d (input pull-down), u (input pull-up), 1x (cmos pad 0.8ma), 8ma (ttl pad) ntest=1 && npllenable=0 pin primary gpio en muxed func. pad direction pad type drive strength function 1 kscani[0] gpioa[0] io 1x matrix keyboard scan bus input 2 kscani[1] gpioa[1] io 1x matrix keyboard scan bus input 3 kscani[2] gpioa[2] io 1x matrix keyboard scan bus input 4 kscani[3] gpioa[3] io 1x matrix keyboard scan bus input 5 kscani[4] gpioa[4] io 1x matrix keyboard scan bus input 6 kscani[5] gpioa[5] io 1x matrix keyboard scan bus input 7 vss 8 vdd 9 kscano[0] gpioa[6] io od 1x matrix keyboard scan bus output 10 kscano[1] gpioa[7] io od 1x matrix keyboard scan bus output 11 kscano[2] gpioa[8] io od 1x matrix keyboard scan bus output 12 kscano[3] gpioa[9] io od 1x matrix keyboard scan bus output 13 kscano[4] gpioa[10] io od 1x matrix keyboard scan bus output 14 kscano[5] gpioa[11] io od 1x matrix keyboard scan bus output 15 tdi i u jtag data input 16 tck i u jtag clock input 17 tms i u jtag mode sel. 18 ntrst i d jtag reset 19 tdo o 1x jtag data output 20 oscin c main oscillator in 21 oscout main oscillator out 22 rtcvdd rtc vdd 23 rtcoscin a rtc oscillator in 24 rtcoscout a rtc oscillator out 25 usbn a usb transceiver neg. data i/o 26 usbp a usb transceiver pos. data i/o 27 usbvss 28 usbvdd 29 pllvss48m 30 pllvdd48m 31 pllvss60m 32 pllvdd60m 33 vsscore a core vss 34 vddcore a core vdd 35 adcvdd 36 adcvref a adc ref. voltage 37 adin[0] a adc data input 38 adin[1] a adc data input 39 adin[2] a adc data input 40 adcvss 41 npmwakeup i su wake-up "on-key" input 42 npor i su power on reset input 43 nreset io u 1x reset input 44 pmbatok i u main battery ok 45 npllenable i pll enable input 46 ntest i u test mode sel. in 47 scrst[0] gpiob[0] uart0rx io od 1x smartcard reset output (uart0 rx) 48 scio[0] gpiob[1] uart0tx io od 1x smartcard data i/o (uart0 tx) 49 vss
signal description magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 22 - ntest=1 && npllenable=0 pin primary gpio en muxed func. pad direction pad type drive strength function 50 vdd 51 scclk[0] gpiob[2] io od 1x smartcard clock output 52 scpres[0] gpiob[3] io 1x smartcard detect input 53 scrst[1] gpiob[4] uart1rx io od 1x smartcard reset output (uart1 rx) 54 scio[1] gpiob[5] uart1tx io od 1x smartcard data i/o (uart1 tx) 55 scclk[1] gpiob[6] io od 1x smartcard clock output 56 scpres[1] gpiob[7] io 1x smartcard detect input 57 uart2rx gpiob[8] io 1x uart2 serial data input 58 uart2tx gpiob[9] io 1x uart2 serial data output 59 uart3rx gpiob[10] io 1x uart3 serial data input 60 uart3tx gpiob[11] io 1x uart3 serial data output 61 irda4rx gpiob[12] uart4rx io 1x irda serial data input (uart4 rx) 62 irda4tx gpiob[13] uart4tx io 1x irda serial data output (uart4 tx) 63 gpiob14 gpiob[14] io 1x general purpose i/o (to deep sleep source) 64 gpiob15 gpiob[15] io 1x general purpose i/o (hotsync wake-up source) 65 touchxp gpiob[16] io 1x touch screen switch x-pos. out 66 vss 67 vdd 68 touchyp gpiob[17] io 1x touch screen switch y-pos. out 69 touchxn gpiob[18] io 1x touch screen switch x-neg. out 70 touchyn gpiob[19] io 1x touch screen switch n-neg. out 71 nuring gpiob[20] io 1x uart5 ring input (wakeup to pmu) 72 nudcd gpiob[21] io 1x uart5 data carrier detect in 73 nudsr gpiob[22] io 1x uart5 data set ready input 74 nucts gpiob[23] io 1x uart5 clear to send input 75 nurts gpiob[24] io 1x uart5 request to send output 76 nudtr gpiob[25] io 1x uart5 data terminal ready out 77 uart5rx gpiob[26] io 1x uart5 serial data input 78 uart5tx gpiob[27] io 1x uart5 serial data output 79 nsmcd gpioc[0] io 1x smc card detect in 80 vsscore 81 vddcore 82 nsmrb gpioc[1] io 1x smc ready/busy in 83 smale gpioc[2] io 1x smc address latch enable output 84 smcle gpioc[3] io 1x smc command latch enable output 85 nsmce gpioc[4] io 1x smc chip en out 86 nsmre gpioc[5] io 1x smc read en out 87 vss 88 vdd 89 nsmwe gpioc[6] io 1x smc write en out 90 nsmwp gpioc[7] io 1x smc write protect output 91 smd[0] gpioc[8] io 1x smc bidir. data i/o 92 smd[1] gpioc[9] io 1x smc bidir. data i/o 93 smd[2] gpioc[10] io 1x smc bidir. data i/o 94 smd[3] gpioc[11] io 1x smc bidir. data i/o 95 smd[4] gpioc[12] io 1x smc bidir. data i/o 96 smd[5] gpioc[13] io 1x smc bidir. data i/o 97 smd[6] gpioc[14] io 1x smc bidir. data i/o 98 smd[7] gpioc[15] io 1x smc bidir. data i/o 99 romswap i swap internal rom / external flashrom 100 bootsel i select bootbus width and direction (smc/mmc) 101 nrcs[0] o 3x rom chip sel. out 102 nrcs[1] o 3x rom chip sel. out
signal description magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 23 - ntest=1 && npllenable=0 pin primary gpio en muxed func. pad direction pad type drive strength function 103 nrcs[2] gpiod[0] io 3x rom chip sel. out 104 nrcs[3] gpiod[1] io 3x rom chip sel. out 105 vss 106 vdd 107 nroe o 3x rom out en out 108 nrwe[0] o 3x rom write en out 109 nrwe[1] o 3x rom write en out 110 rd[0] sd[0] io 8ma rom bidir. data i/o 111 rd[1] sd[1] io 8ma rom bidir. data i/o 112 rd[2] sd[2] io 8ma rom bidir. data i/o 113 rd[3] sd[3] io 8ma rom bidir. data i/o 114 rd[4] sd[4] io 8ma rom bidir. data i/o 115 rd[5] sd[5] io 8ma rom bidir. data i/o 116 rd[6] sd[6] io 8ma rom bidir. data i/o 117 rd[7] sd[7] io 8ma rom bidir. data i/o 118 rd[8] sd[8] io 8ma rom bidir. data i/o 119 vss 120 vdd 121 rd[9] sd[9] io 8ma rom bidir. data i/o 122 rd[10] sd[10] io 8ma rom bidir. data i/o 123 rd[11] sd[11] io 8ma rom bidir. data i/o 124 rd[12] sd[12] io 8ma rom bidir. data i/o 125 rd[13] sd[13] io 8ma rom bidir. data i/o 126 rd[14] sd[14] io 8ma rom bidir. data i/o 127 rd[15] sd[15] io 8ma rom bidir. data i/o 128 ra[0] sa[0] io 8ma rom address out 129 ra[1] sa[1] io 8ma rom address out 130 ra[2] sa[2] io 8ma rom address out 131 ra[3] sa[3] io 8ma rom address out 132 vsscore 133 vddcore 134 vss 135 vdd 136 ra[4] sa[4] io 8ma rom address out 137 ra[5] sa[5] io 8ma rom address out 138 ra[6] sa[6] io 8ma rom address out 139 ra[7] sa[7] io 8ma rom address out 140 ra[8] sa[8] io 8ma rom address out 141 ra[9] sa[9] io 8ma rom address out 142 sa10 sa[10] o 8ma rom address out 143 ra[10] io 8ma rom address out 144 ra[11] sa[11] io 8ma rom address out 145 ra[12] sa[12] io 8ma rom address out 146 vss 147 vdd 148 ra[13] sa[13] io 8ma rom address out 149 ra[14] sa[14] io 8ma rom address out 150 ra[15] io 8ma rom address out 151 ra[16] o 8ma rom address out 152 ra[17] o 8ma rom address out 153 ra[18] o 8ma rom address out 154 ra[19] o 8ma rom address out 155 ra[20] o 8ma rom address out
signal description magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 24 - ntest=1 && npllenable=0 pin primary gpio en muxed func. pad direction pad type drive strength function 156 ra[21] o 8ma rom address out 157 ra[22] o 8ma rom address out 158 ra[23] o 8ma rom address out 159 vss 160 vdd 161 dqml gpiod[2] io 8ma sdram lower data mask output 162 dqmu gpiod[3] io 8ma sdram upper data mask output 163 nswe gpiod[4] io 8ma sdram write enable output 164 ncas gpiod[5] io 8ma sdram column address select out 165 nras gpiod[6] io 8ma sdram row address select out 166 nscs[0] gpiod[7] io 8ma sdram chip select output 167 nscs[1] gpiod[8] io 8ma sdram chip select output 168 scke[0] gpiod[9] io 8ma sdram clock enable output 169 scke[1] gpiod[10] io 8ma sdram clock enable output 170 vss 171 sclk io 8ma sdram clock i/o (for fbclk) 172 vdd 173 llp gpiod[11] io 1x lcd line pulse 174 lac gpiod[12] io 1x lcd ac bias 175 lblen gpiod[13] io 1x lcd back-light en 176 lcp gpiod[14] io 1x lcd clock pulse 177 lfp gpiod[15] io 1x lcd frame pulse 178 lcden gpiod[16] io 1x lcd display en 179 ld[0] gpiod[17] io 1x lcd data bus 180 ld[1] gpiod[18] io 1x lcd data bus 181 ld[2] gpiod[19] io 1x lcd data bus 182 ld[3] gpiod[20] io 1x lcd data bus 183 ld[4] gpiod[21] io 1x lcd data bus 184 vsscore 185 vddcore 186 ld[5] gpiod[22] io 1x lcd data bus 187 ld[6] gpiod[23] io 1x lcd data bus 188 ld[7] gpiod[24] io 1x lcd data bus 189 spirx[0] gpioe[0] io 1x spi data in 190 vss 191 vdd 192 spitx[0] gpioe[1] io 1x spi data output 193 nspics[0] gpioe[2] io 1x spi chip select 194 spiclk[0] gpioe[3] io 1x spi clock output 195 spirx[1] gpioe[4] io 1x spi data in 196 spitx[1] gpioe[5] io 1x spi data output 197 nspics[1] gpioe[6] io 1x spi chip select 198 spiclk[1] gpioe[7] io 1x spi clock output 199 2wsiclk gpioe[8] io od 1x 2wsi clock i/o 200 2wsidat gpioe[9] io od 1x 2wsi data i/o 201 timer[0] gpioe[10] io 1x timer data output 202 timer[1] gpioe[11] io 1x timer data output 203 timer[2] gpioe[12] io 1x timer data output 204 timer[3] gpioe[13] io 1x timer data output 205 pwm[0] gpioe[14] io 1x pwm data output 206 pwm[1] gpioe[15] io 1x pwm data output 207 testscan i d test signal input 208 scanen i d test signal input
arm720t macrocell magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 25 - 3 arm720t macrocell 3.1 arm720t macrocell for details of the arm720t, please refer to the arm720t data sheet (ddi 0087).
arm720t macrocell magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 26 -
memory map magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 27 - 4 memory map there are five main memory map divisions, outlined in table 4-1 top-level address map function base address (hex) size description internal boot rom / external static memory (romswap = 0) 0x0000.0000 0x0000 0800 0x0100 0000 0x0200 0000 0x0300 0000 0x0400 0000 0x1000.0000 0x1100 0000 2 kbytes -- 16 mbytes 16 mbytes 16 mbytes -- 16 mbytes -- internal boot rom reserved external static memory chip select 1 external static memory chip select 2 external static memory chip select 3 reserved external static memory chip select 0 reserved internal boot rom / external static memory (romswap = 1) 0x0000.0000 0x0100 0000 0x0200 0000 0x0300 0000 0x0400 0000 0x1000.0000 0x1000 0800 16 mbytes 16 mbytes 16 mbytes 16 mbytes -- 2 kbytes -- external static memory chip select 0 external static memory chip select 1 external static memory chip select 2 external static memory chip select 3 reserved internal boot rom reserved internal sram 0x3000 0000 0x3fff.e000 - 8 kbytes reserved internal sram external sdram 0x4000.0000 0x4200.0000 0x4400.0000 0x4600.0000 0x4800 0000 32 mbytes 32 mbytes -- -- -- sdram chip select 0 sdram chip select 1 sdram mode register chip 0 sdram mode register chip 1 reserved peripherals 0x8000.0000 0x8006 3000 -- -- asb, apb peripherals reserved table 4-1 top-level address map when a romswap pin is set low, if a bootsel pin is set high, the smc(nand flash) can be used by connecting to ebi, and if a bootsel pin is set low, the mmc can be used by connecting to ssi 0. when a romswap pin is set high, if a bootsel pin is set high, support external 16-bit memory, and if a boorsel pin is set low, support external 8-bit memory booting, the external static memory has an address space of 64mbytes that is split equally between four external static memory chip select. actual address range for each chip select is 16mbytes with 24 external address signals.
memory map magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 28 - extrnal memory + internal rom external memory reserved 0x1000 0000 0x0000 0000 0x2000 0000 0x3000 0000 internal sram external sdram 0x4000 0000 reserved 0x5000 0000 reserved 0x6000 0000 reserved 0x7000 0000 internal peripherals 0x8000 0000 reserved 0x9000 0000 0xffff ffff boot rom (2kb) 0x0000 0000 reserved 0x0000 0800 0x0100 0000 ncs2 (16mb) 0x0200 0000 ncs1 (16mb) ncs3 (16mb) 0x0300 0000 reserved 0x0300 0000 ncs0 (16mb) 0x1000 0000 reserved 0x0300 0000 extrnal memory + internal rom external memory reserved 0x1000 0000 0x0000 0000 0x2000 0000 0x3000 0000 internal sram external sdram 0x4000 0000 reserved 0x5000 0000 reserved 0x6000 0000 reserved 0x7000 0000 internal peripherals 0x8000 0000 reserved 0x9000 0000 0xffff ffff boot rom (2kb) 0x0000 0000 reserved 0x0000 0800 0x0100 0000 ncs2 (16mb) 0x0200 0000 ncs1 (16mb) ncs3 (16mb) 0x0300 0000 reserved 0x0300 0000 ncs0 (16mb) 0x1000 0000 reserved 0x0300 0000 figure 4-1. internal boot rom / external static memory map (romswap=0)
memory map magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 29 - external memory internal boot rom reserved 0x1000 0000 0x0000 0000 0x2000 0000 0x3000 0000 internal sram external sdram 0x4000 0000 reserved 0x5000 0000 reserved 0x6000 0000 reserved 0x7000 0000 internal peripherals 0x8000 0000 reserved 0x9000 0000 0xffff ffff boot rom (2kb) 0x0000 0000 0x1000 0800 0x0100 0000 ncs2 (16mb) 0x0200 0000 ncs1 (16mb) ncs3 (16mb) 0x0300 0000 reserved 0x0300 0000 ncs0 (16mb) 0x1000 0000 reserved external memory internal boot rom reserved 0x1000 0000 0x0000 0000 0x2000 0000 0x3000 0000 internal sram external sdram 0x4000 0000 reserved 0x5000 0000 reserved 0x6000 0000 reserved 0x7000 0000 internal peripherals 0x8000 0000 reserved 0x9000 0000 0xffff ffff boot rom (2kb) 0x0000 0000 0x1000 0800 0x0100 0000 ncs2 (16mb) 0x0200 0000 ncs1 (16mb) ncs3 (16mb) 0x0300 0000 reserved 0x0300 0000 ncs0 (16mb) 0x1000 0000 reserved figure 4-2. internal boot rom / external static memory map (romswap=1)
memory map magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 30 - there is a maximum of 64mbytes of sdram space. the mode registers (in the sdram) are programmed by reading from 64mbyte address space immediately above the sdram (over 0x4400.0000). reserved 0x1000 0000 0x0000 0000 0x2000 0000 0x3000 0000 internal sram external sdram 0x4000 0000 reserved 0x5000 0000 reserved 0x6000 0000 reserved 0x7000 0000 internal peripherals 0x8000 0000 reserved 0x9000 0000 0xffff ffff 0x3000 0000 0x3fff e000 0x4000 0000 reserved internal sram (8kb) nscs1 (32mb) 0x4200 0000 0x4400 0000 nscs0 (32mb) sdram mode register 1 0x4600 0000 0x4800 0000 sdram mode register 0 reserved 0x5000 0000 reserved 0x1000 0000 0x0000 0000 0x2000 0000 0x3000 0000 internal sram external sdram 0x4000 0000 reserved 0x5000 0000 reserved 0x6000 0000 reserved 0x7000 0000 internal peripherals 0x8000 0000 reserved 0x9000 0000 0xffff ffff 0x3000 0000 0x3fff e000 0x4000 0000 reserved internal sram (8kb) nscs1 (32mb) 0x4200 0000 0x4400 0000 nscs0 (32mb) sdram mode register 1 0x4600 0000 0x4800 0000 sdram mode register 0 reserved 0x5000 0000 figure 4-3. internal sram / external sdram memory map
memory map magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 31 - the peripheral address space is subdivided into two main areas: those on the asb, the apb. the base address for the peripherals is given in table 4-2: peripherals base addresses. function base address (hex) name description 0x8000.0000 sdramc base sdram controller 0x8001.0000 pmu base pmu 0x8002.0000 extflashc base external bus interface 0x8003.0000 reserved asb peripherals 0x8004.0000 armtest base to arm cpu 0x8005.0000 intc base interrupt controller 0x8005.1000 usb base usb controller 0x8005.2000 lcd base lcd controller 0x8005.3000 adc base adc interface 0x8005.4000 uart0 base uart0 (sci0) 0x8005.5000 uart1 base uart1 (sci1) 0x8005.6000 uart2 base uart2 0x8005.7000 uart3 base uart3 0x8005.8000 uart4 base uart4 (sir) 0x8005.9000 uart5 base uart5 (modem) 0x8005.a000 ssi0 base ssi 0 0x8005.b000 ssi1 base ssi 1 0x8005.c000 smc base smc 0x8005.d000 tim base timerx4 / pwmx2 0x8005.e000 wdt base wdt 0x8005.f000 rtc base rtc 0x8006.0000 2wsbi base 2wsbi 0x8006.1000 kbd base matrix keyboard apb peripherals 0x8006.2000 gpio base gpio table 4-2 peripherals base addresses
memory map magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 32 - reserved 0x1000 0000 0x0000 0000 0x2000 0000 0x3000 0000 internal sram external sdram 0x4000 0000 reserved 0x5000 0000 reserved 0x6000 0000 reserved 0x7000 0000 internal peripherals 0x8000 0000 reserved 0x9000 0000 0xffff ffff sdramc 0x8000 0000 pmu 0x8001 0000 ebi 0x8002 0000 reserved 0x8003 0000 arm test 0x8004 0000 intc 0x8005 0000 usb 0x8005 1000 lcd 0x8005 2000 adc 0x8005 3000 sci 0 / uart 0 0x8005 4000 sci 1 / uart 1 0x8005 5000 uart 2 0x8005 6000 uart 3 0x8005 7000 uart 4 0x8005 8000 uart 5 0x8005 9000 ssi 0 0x8005 a000 ssi 1 0x8005 b000 smc 0x8005 c000 timer / pwm 0x8005 d000 wdt 0x8005 e000 rtc 0x8005 f000 2-wire sbi 0x8006 0000 keyboard 0x8006 1000 gpio 0x8006 2000 reserved 0x8006 3000 0x8fff ffff reserved 0x1000 0000 0x0000 0000 0x2000 0000 0x3000 0000 internal sram external sdram 0x4000 0000 reserved 0x5000 0000 reserved 0x6000 0000 reserved 0x7000 0000 internal peripherals 0x8000 0000 reserved 0x9000 0000 0xffff ffff sdramc 0x8000 0000 pmu 0x8001 0000 ebi 0x8002 0000 reserved 0x8003 0000 arm test 0x8004 0000 intc 0x8005 0000 usb 0x8005 1000 lcd 0x8005 2000 adc 0x8005 3000 sci 0 / uart 0 0x8005 4000 sci 1 / uart 1 0x8005 5000 uart 2 0x8005 6000 uart 3 0x8005 7000 uart 4 0x8005 8000 uart 5 0x8005 9000 ssi 0 0x8005 a000 ssi 1 0x8005 b000 smc 0x8005 c000 timer / pwm 0x8005 d000 wdt 0x8005 e000 rtc 0x8005 f000 2-wire sbi 0x8006 0000 keyboard 0x8006 1000 gpio 0x8006 2000 reserved 0x8006 3000 0x8fff ffff figure 4-4. peripherals address map
internal boot rom magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 33 - 5 internal boot rom HMS30C7210 has internal boot rom. boot rom?s role load user?s image code from external ebi nand flash / mmc connected ssi to internal sram (8kbytes) and jumps to user?s image code at internal sram. like previous explanation, HMS30C7210 has two internal booting modes [ nand / mmc ]. each mode setting is decided as two external pin [ romswap (99), bootsel (100) ] states. initially contents of copied image code from nand / mmc to internal sram are sdram initialization routine, copy routine from boot loader or executive binary image to sdram and jump to sdram starting address. 5.1 hardware setting HMS30C7210 can boot internal boot rom [romswap=0] and external memory [romswap=1]. if it is set to internal boot rom, it can be nand [bootsel=1]/mmc [bootsel=0] boot mode setting. romswap bootsel boot mode low (=0) mmc low (=0) high (=1) nand low (=0) 8 bit high (=1) high (=1) 16 bit table 5-1. pin configuration
internal boot rom magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 34 - 5.2 software setting if it is decided on internal booting mode at h/w, you can program code to copy from nand/mmc to internal sram. internal sram has 8kbytes. so size of code, data and stack don?t have over 8kbytes. presently code and data size is max. 7.5kbytes, stack size can use 0.5kbytes. following figure show s/w flows. figure 5-1. software boot flows ? after power on, internal boot rom copies executive code (nand/mmc address 0x00) from nand/mmc to internal sram. ? internal sram code from nand/mmc has sdram controller initialization routine, copy other executive binary code from nand/mmc to sdram and jump to sdram start address. used nand/mmc map is following table. address discription 0x0000 0000 ~ 0x0000 3fff boot 0 (no change) iram2dram.axf 0x0000 4000 ~ 0x0000 7fff boot 1 (no change) iram2dram.axf 0x0000 8000 ~ binary image (sdram no initialization) table 5-2. nand / mmc map there are boot0, boot1 area in nand/mmc. if boot0 don?t operate correctly, boot rom uses boot1 area in internal boot program. also user?s binary program don?t initialize sdram init routine.
internal boot rom magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 35 -

pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 37 - 6 pmu & pll the HMS30C7210 is designed primarily for smart card reader and other portable computing applications. therefore there are 4 operating modes to reduce power consumption and extend battery life. ? run - normal operation (typically used for cpu-intensive tasks). ? slow - half-speed operation used in the application demanding low computing power. ? idle - where the cpu operation is halted but peripherals continue their operations (such as screen refresh, or serial communications). ? sleep & deep sleep - this mode will be perceived as `off' by the user, but the sdram contents are preserved and only the real-time clock is running. the transition between these modes is controlled by the pmu (see also section 6.4 power management). the pmu is an asb slave unit to allow the cpu to access (read/write) its control registers, and is an asb master unit to provide the mechanism for stopping the arm core's internal clock. clock & reset gen. osc asb i/f fsm pmu registers 6 mhz external i/f nreset npor npmwakeup clk32khz pmbatok portb[15:14] asb interface wdtrst nirq/nfiq wake-up event sreqref/sackref fpll (60mhz) cpll (48mhz) fclkout bclkout vclkout cclkout qclkraw pclkraw bnresout /2 /13 /13.5 mux figure 6-1. pmu block diagram
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 38 - 6.1 external signals pin name type description npor is power on reset input. schmitt level input with pull-up npmwakeup is wake-up ?on-key? input. nreset i/o reset input pmbatok i main battery ok gpiob[14] i to-deep-sleep input from gpiob[14] gpiob[15] i hotsync request from portb[15] refer to figure 2-1. 208 pin diagram. 6.2 registers address name width default description 0x8001.0000 pmumr 4 0x0 pmu mode register 0x8001.0010 pmuidr 32 0x0072100 pmu id register 0x8001.0020 pmursr 27 - pmu reset/status register 0x8001.0028 pmuccr 16 0x2f pmu clock control register 0x8001.0030 pmudctr 18 - pmu debounce counter test register 0x8001.0038 pmutr 8 0x0 pmu test register table 6-1. pmu register summary
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 39 - 6.2.1 pmu mode register (pmumr) this read/write register is to change from run mode or slow mode into a different mode. the pmu mode encoding is shown below. the register can only be accessed in run mode or slow mode (these are the only modes in which the processor is active). therefore, the processor will never be able to read values for modes other than mode 0x00 and mode 0x01. a test controller may read other values as long as clocks are enabled in every pmu mode by the bit 8 of the pmu debounce counter test register (pmudctr). for more information, please refer to 6.2.5 . 0x80010000 31 ? 3 2 1 0 reserved reserved wakeup ctrl modesel[2:0] bits type function 31:4 - reserved 3 r/w wake-up control 0 = prevent the pmu from exiting the deep sleep mode when the pin pmbatok is inactive. 1 = allow the pmu to exit the deep sleep mode even if the pin pmbatok is inactive. 2:0 r/w mode selection in reads, the read value is the current pmu mode. in writes, the write value is the target mode at which the pmu will arrive eventually. value pmu mode encoding 0x04 initialization mode 0x01 run mode 0x00 slow mode 0x02 idle mode 0x03 sleep mode 0x07 deep sleep mode note all other values in the above table are undefined. 6.2.2 pmu id register (pmuid) this read-only register returns a unique chip revision id. revision 0 of the HMS30C7210 device (the first revision) will return the constant value 0x00721000. 0x80010010 31 ? 0 0x00721000
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 40 - 6.2.3 pmu reset/status register (pmursr) this read/write register provides information on power-on reset and the pll status as well as wakeup and interrupt events. the pmursr also provides software-initiated warm reset, and wakeup and interrupt masking the allocation is shown in the following two tables: pmursr bits. the event bits in this register are `sticky' bits. for a definition of a sticky bit, please refer to 5.2.3 wake-up debounce and interrupt. generally, this register will be read each time the arm exits from reset mode, so that the arm can identify what event has caused it to exit from reset mode. 0x80010020 31 30 29 28 27 26 25 24 reserved reserved reserved reserved reserved warm reset hotsync dben warm rst dben 23 22 21 20 19 18 17 16 pfail dben mring dben onkey dben hotsync waken warm rst waken rtc waken mring waken onkey waken 15 14 13 12 11 10 9 8 hotsync intren pfail intren rtc intren mring intren onkey intren hotsync evt wdt rst evt warm rst evt 7 6 5 4 3 2 1 0 pfail evt rtc evt mring evt onkey evt fpll un-lock cpll un-lock deep evt por evt bits type function 31:27 - reserved 26 w software warm reset. writing a `1' to this bit causes nreset and the asb system reset to be asserted. writing a `0' to this bit has no effect. 25 r/w debounce enable of hot sync event. 0 = disable debouncing of hot sync event. 1 = enable debouncing of hot sync event (default). 24 r/w debounce enable of warm reset event. 0 = disable debouncing of warm reset event. 1 = enable debouncing of warm reset event (default). 23 r/w debounce enable of power fail event. 0 = disable debouncing of power fail event. 1 = enable debouncing of power fail event (default). 22 r/w debounce enable of modem ring indicator event. 0 = disable debouncing of modem ring indicator event. 1 = enable debouncing of modem ring indicator event (default). 21 r/w debounce enable of on key event. 0 = disable debouncing of on key event. 1 = enable debouncing of on key event (default). 20 r/w wake-up enable of hot sync event. 0 = disable cpu wake-up due to hot sync event (default). 1 = enable cpu wake-up due to hot sync event. 19 r/w wake-up enable of external warm reset event. 0 = disable cpu wake-up due to external warm reset event (default). 1 = enable cpu wake-up due to external warm reset event. 18 r/w wake-up enable of rtc alarm event 0 = disable cpu wake-up due to rtc alarm event (default). 1 = enable cpu wake-up due to rtc alarm event. 17 r/w wake-up enable of modem ring indicator event 0 = disable cpu wake-up due to modem ring indicator event (default). 1 = enable cpu wake-up due to modem ring indicator event. 16 r/w wake-up enable of on key event. 0 = disable cpu wake-up due to on key event (default). 1 = enable cpu wake-up due to on key event.
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 41 - 15 r/w interrupt mask of hot sync event. 0 = disable pmu interrupt due to hot sync event (default). 1 = enable pmu interrupt due to hot sync event. 14 r/w interrupt mask of power fail event. 0 = disable pmu interrupt due to power fail event (default). 1 = enable pmu interrupt due to power fail event. 13 r/w interrupt mask of rtc alarm event 0 = disable pmu interrupt due to rtc alarm event (default). 1 = enable pmu interrupt due to rtc alarm event. 12 r/w interrupt mask of modem ring indicator event 0 = disable pmu interrupt due to modem ring indicator event (default). 1 = enable pmu interrupt due to modem ring indicator event. 11 r/w interrupt mask of on key event 0 = disable pmu interrupt due to on key event (default). 1 = enable pmu interrupt due to on key event. 10 r/w hot sync event (irq from gpiob[15]) in reads, 0 = no hot sync event has occurred since last cleared; 1 = hot sync event has occurred since last cleared. in writes, writing a `1' to this bit causes it to be cleared. when set, a pmu interrupt is generated if pmursr[15] (hotsync intren) is also set. 9 r/w watch dog timer reset event (a kind of warm reset) in reads, 0 = no watch dog timer reset event has occurred since last cleared; 1 = watch dog timer reset event has occurred since last cleared. in writes, writing a `1' to this bit causes it to be cleared. 8 r/w warm (external or software) reset event in reads, 0 = no warm reset event has occurred since last cleared; 1 = warm reset event has occurred since last cleared. in writes, writing a `1' to this bit causes it to be cleared. 7 r/w power fail event (adaptor not ok, low pmbatok) in reads, 0 = no power fail event has occurred since last cleared; 1 = power fail event has occurred since last cleared. in writes, writing a `1' to this bit causes it to be cleared. when set, a pmu interrupt is generated if pmursr[14] (pfail intren) is also set. 6 r/w rtc (real time clock) alarm event in reads, 0 = no rtc alarm event has occurred since last cleared; 1 = rtc alarm event has occurred since last cleared. in writes, writing a `1' to this bit causes it to be cleared. when set, a pmu interrupt is generated if pmursr[13] (rtc intren) is also set. 5 r/w modem ring indicator event (low nmring) in reads, 0 = no modem ring indicator event has occurred since last cleared; 1 = modem ring indicator event has occurred since last cleared. in writes, writing a `1' to this bit causes it to be cleared. when set, a pmu interrupt is generated if pmursr[12] (mring intren) is also set. 4 r/w on key event (low npmwakeup) in reads, 0 = no on key event has occurred since last cleared; 1 = on key event has occurred since last cleared. in writes, writing a `1' to this bit causes it to be cleared. when set, a pmu interrupt is generated if pmursr[11] (onkey intren) is also set 3 r/w fclk pll un-lock event in reads, 0 = fclk pll has been locked since last cleared; 1 = fclk pll has fallen out of lock since last cleared. in writes, writing a `1' to this bit causes it to be cleared. 2 r/w cclk pll un-lock event in reads,
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 42 - 0 = cclk pll has been locked since last cleared; 1 = cclk pll has fallen out of lock since last cleared. in writes, writing a `1' to this bit causes it to be cleared. 1 r/w deep sleep event in reads, 0 = pmu has not entered the deep sleep mode since last cleared; 1 = pmu has entered the deep sleep mode since last cleared. in writes, writing a `1' to this bit causes it to be cleared. 0 r/w power-on reset event in reads, 0 = no power-on reset event has occurred since last cleared; 1 = power-on reset event has occurred since last cleared. in writes, writing a `1' to this bit causes it to be cleared.
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 43 - 6.2.4 pmu clock control register (pmuccr) this register is used to control the two plls (fclk and cclk plls) and three main clocks (fclk, cclk and vclk). the six bits of the pmuccr are used to compose the input pins of the fclk pll for frequency selection and thus define the frequency of the fclk. the default value (after power-on reset) for this register is 0x2f. 0x80010028 15 14 13 12 11 10 9 8 cclk enable vclk enable vclk sel reserved reserved reserved reserved reserved 7 6 5 4 3 2 1 0 fclk mute ctrl ffreq update ctrl fclk pll freq[5:0] bits type function 31:16 - reserved 15 r/w cclk enable 0 = the cclk is disabled. 1 = the cclk is enabled. 14 r/w vclk enable 0 = the vclk is disabled. 1 = the vclk is enabled. 13 r/w vclk select 0 = the vclk uses the clock source of the fclk as its clock source. 1 = the vclk uses the clock source of the cclk as its clock source. 12:8 r/w reserved 7 r/w fclk mute control 0 = the fclk is muted when the fclk pll is out of lock. 1 = the fclk is only muted during power-on reset. subsequent unlock condition does not mute the fclk. allows dynamic changes to the clock frequency without halting execution. care: this only will be legal if fclk pll is under-damped (i.e. will not exhibit overshoot in its lock behavior). 6 r/w fclk pll frequency update control 0 = the written value to the bits[5:0] of the pmuccr is transferred to a 6-bit temporary register, not the pmuccr[5:0]. after that, if the cpu enters the deep sleep mode, the value in the temporary register is transferred to the bits[5:0] of the pmuccr and thus the frequency control of the fclk pll is updated. and then, the fclk pll comes to life with the new frequency when the cpu exits the deep sleep mode. 1 = the pmuccr[5:0] and the frequency of the fclk pll is updated immediately after writing to the pmuccr[5:0]. 5:0 r/w fclk pll frequency control value frequency bit[5]= 0 0x0c 21 mhz 0x0d 22.5 mhz 0x0e 24 mhz 0x0f 25.5 mhz 0x10 27 mhz 0x11 28.5 mhz 0x12 30 mhz 0x13 31.5 mhz 0x14 33 mhz 0x15 34.5 mhz 0x16 36 mhz 0x17 37.5 mhz 0x18 39 mhz 0x19 40.5 mhz 0x1a 42 mhz
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 44 - 0x1b 43.5 mhz 0x1c 45 mhz 0x1d 46.5 mhz 0x1e 48 mhz unpredictable otherwise value frequency bit[5] = 1 0x25 21 mhz 0x26 24 mhz 0x27 27 mhz 0x28 30 mhz 0x29 33 mhz 0x2a 36 mhz 0x2b 39 mhz 0x2c 42 mhz 0x2d 45 mhz 0x2e 48 mhz 0x2f 51 mhz (default) 0x30 54 mhz 0x31 57 mhz 0x32 60 mhz 0x33 63 mhz 0x34 66 mhz 0x35 69 mhz 0x36 72 mhz 0x37 75 mhz 0x38 78 mhz 0x39 81 mhz 0x3a 84 mhz 0x3b 87 mhz 0x3c 90 mhz 0x3d 93 mhz 0x3e 96 mhz unpredictable otherwise if bit 6 (fclk frequency update control) is `0' when the cpu core writes to bits[5:0] of this register, these bits are stored in a temporary buffer, which is not transferred to the input pins of the fclk pll until the next time the cpu enters the deep sleep mode. this means that for a new value to take effect, it is necessary for the device to enter the deep sleep mode first. if bit 6 (fclk frequency update control) is `1' the first effect that writing a new value to bits [5:0] will have is that the fclk pll will go out of lock, and the clock control circuit will immediately inhibit fclk and bclk, without first verifying that sdram operations have completed.
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 45 - 6.2.5 pmu debounce counter test register (pmudctr) 0x80010030 23 22 21 20 19 18 17 16 reserved reserved reserved reserved reserved reserved rst db ctrl clk32k extsel 15 14 13 12 11 10 9 8 dbgpioa dbsel[3:0] clk15 clk31 clk62 7 6 5 4 3 2 1 0 clk125 clk500 clk1k clk2k clk4k dbcnt[2:0] function bits type read write 31:18 - reserved 17 r warm reset debounce time control this is set to the same value of the pin tdi (input with a pull-up resistor) during power-on reset. 0 = debouncing time of warm reset (or power on reset) is short since the debounce counter uses 16-khz clock. 1 = debouncing time of warm reset (or power on reset) is long since the debounce counter uses 15.625-hz clock (default). 16 r/w external clk32k select 0 = use the rtc clock as the 32-khz input clock. 1 = use the external clock (from the tbfclk pin) as the 32-khz input clock in the tic test mode (ntest = ?0?) to test the frequency-division circuit making the debounce clock. 15 r/w gpioa debounce counter select 0 = select a debounce counter other than gpioa debounce counters as the bits[2:0] of pmudctr in read. 1 = select one among gpioa debounce counters as the bits[2:0] of the pmudctr in read. 14:11 r/w debounce counter select when dbgpioa (pmudctr[15]) is reset value function 0x0 on key event 0x1 modem ring indicator event 0x2 power fail event 0x3 warm reset event 0x4 hot sync event (gpiob[15]) 0x5 todeepsleep event (gpiob[14]) unpredictable otherwise. when dbgpioa (pmudctr[15]) is set, value function 0x0 gpioa[0] 0x1 gpioa[1] 0x2 gpioa[2] 0x3 gpioa[3] 0x4 gpioa[4] 0x5 gpioa[5] 0x6 gpioa[6] 0x7 gpioa[7] 0x8 gpioa[8] 0x9 gpioa[9] 0xa gpioa[10] 0xb gpioa[11] 10 r 15.625-hz clk 15.625-hz debouncing clk derived from the rtc clock. this clock is used to debounce on key, warm reset, hot sync, todeepsleep events and gpioa values. 9 r 31.25-hz clk 31.25-hz clk derived from the rtc clock.
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 46 - 8 r 62.5-hz clk 62.5-hz clk derived from the rtc clock. 7 r 125-hz clk 125-hz clk derived from the rtc clock. 6 r 500-hz clk 500-hz clk derived from the rtc clock. 5 r 1-khz clk 1-khz clk derived from the rtc clock. 4 r 2-khz clk 2-khz clk derived from the rtc clock. 3 r 4-khz clk 4-khz clk derived from the rtc clock. 2:0 r selected debounce counter debounce counter selected by the bits[15:11] of the pmudctr. in order that the debounce counters (which would normally be clocked at 250 hz or 15.625 hz) may be independently exercised and observed, the counters may be triggered and observed using the above registers. this register is for the test purpose only and not required in normal use.
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 47 - 6.2.6 pmu test register (pmutr) this register is used to control the pmu operation in the tic test mode. this register is for test purpose only and not required in normal use. 0x80010038 7 6 5 4 3 2 1 0 clk bypass npllen[1:0] pqclk bypass ctrl cclk bypass select bclk bypass clk enforce pmutest bits type function 31:8 - reserved 7 r clock bypass enable read value is the same value of the input pin npllenable if this value is ?1?, the clocks (of the system, usb, lcd, etc.) are provided using external bypass clocks from the pins. normal, this value is ?0?, and the clocks are made using pll output clocks. 6:5 r intermediate pll enable. when the bit[7] and bit[6] (npllen[1]) of this register are both zero, the plls (fpll and cpll) are enabled. 4 r/w pclk/qclk bypass control 0 = when npllenable is ?1?, the pclk and qclk are directly bypassed from pin pads. 1 = when npllenable is ?1?, the pclk and qclk are provided by a frequency divider that uses the bypass clock of the cclk as its source clock. 3 r/w bypass clock select for the cclk 0 = cclk uses tbqfclk, as bypass clocks used when the npllenable pin is reset. 1 = cclk uses tbcclk, as bypass clocks used when the npllenable pin is reset, in the tic test mode. 2 r/w bclk bypass enable 0 = bclk is derived from the fclkq (clock lagging behind the fclk by 90 degrees). 1 = bclk is derived from the bypass clock tbbclk in the tic test mode. 1 r/w clock enforce 0 = the fclk, bclk, vclk and cclk are disabled in the deep sleep mode (normal). 1 = the fclk, bclk, vclk and cclk are enabled regardless of the pmu states (even in the deep sleep mode) in the tic test mode. 0 r/w pmutest 0 = the pmu has lower priority than the tic controller in the asb ownership arbitration. 1 = the pmu has higher priority than the tic controller in the asb ownership arbitration in the tic test mode (for the purpose of tic-testing the pmu).
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 48 - 6.3 pmu functions clock generator the clock generator in the pmu is responsible for controlling the plls and masking clocks by and-gating while the pll outputs are unstable, and ensures that clocks are available during test modes and during reset sequences. fclk (arm processor and sdram controller clock) this clock is derived from the fclk pll (fpll) whose frequency is programmable between 21 mhz and 96 mhz using the lsb 6 bits of the pmuccr (pmu clock control register). its default frequency is 51 mhz. there are two methods for updating frequency, depending upon the state of the bit 6 of the pmuccr (see pmuccr register on section 5.3.4). if the bit 6 is set, then any data written to the bits [5:0] of the pmuccr are immediately transferred to the pins of fpll, thus causing the loop to unlock and to mute fclk. this is only a safe mode of operation if fpll frequency and mark-space ratio is guaranteed to be within limits immediately after lock time. if the bit 6 is not set, then the HMS30C7210 must enter deep sleep mode before the written bits [5:0] of the pmuccr register are transferred to the fpll. to switch between the two frequencies when the bit 6 is not set: ? software writes the new value into the pmuccr register. ? set a real time clock (rtc) alarm to wake up the HMS30C7210 in 2 seconds. ? enter deep sleep mode by writing 0x7 to the bits [2:0] of the pmu mode register (pmumr). ? the HMS30C7210 will resurrect with fpll running at the new frequency by the preset rtc alarm.
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 49 - to switch between the two frequencies when the bit 6 is set and bit 7 is not set: ? software writes the new value into the pmuccr register. ? changes to the clock frequency with program halting execution. ? after fpll state is stable, program is executed. (so you don?t need to check fpll lock bit state) to switch between the two frequencies when the bit 6 is set and bit 7 is set: ? software writes the new value into the pmuccr register. ? changes to the clock frequency without program halting execution. for final switch methode has unstable state(program is not stopped). if you want to check fpll stable state, write ?1? bit in fpll lock bit (it to be cleared) and read fpll lock bit. if fpll lock bit is ?1?, state is unstable. if fpll lock bit is ?0?, state is stable. unknown unstabled clock range fpll lock bit (mute=0) fclk (mute=0) fclk (mute=1) 0x2f (51mhz) 0x32 (60mhz) fclk freq write ? 1 ? is executed here unknown fpll lock bit (mute=1) write ? 1 ? is executed here, but not cleared. figure 6-2. fclk frequency update when the bit 6 is set bclk this clock is asb system bus clock generated by the pmu through dividing the fclk frequency by 2 and 1/4 phase shift. fclk bclk figure 6-3. fclk / bclk relation
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 50 - cclk the cclk is generated by the cpll and the frequency is fixed 48mhz. this clock is only used for the usb. the cclk is disabled when bnres (system reset) is active or when the pmu is put into deep sleep mode. on exit from either of these conditions, the cclk must be re-enabled by software. vclk the vclk is selected between the fpll and cpll clock outputs using the bit 13 of the pmuccr (the vclk uses the fpll output by default), and clocks the lcd controller. the vclk is disabled when bnres is active or when the pmu is put into deep sleep mode. on exit from either of these conditions, the vclk must be re- enabled by software. changing clock (pll) selection: ? software must first disable the vclk, by writing `0' to the bit 14 of the pmuccr register. ? modify the bit 13 of the pmuccr. ? re-enable the vclk by writing ?1? to the bit 14 of the pmuccr register. pclk the pclk is generated the cpll divied by 13 (cpll / 13 = 3.692308mhz). this clock is used for apb block function (uart, wdt, timer etc). qclk the qclk is generated the cpll divied by 13.5 (cpll / 13.5 = 3.555556mhz). this clock is only used for the smartcard interface. pmu state machine the state machine handles the transition between the power management states described below. the cpu can write to the pmu mode registers (which is what would typically happens when a user switches off the device) and the state machine will proceed to the commanded state.
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 51 - 6.4 power management 6.4.1 state diagram figure 6-4. pmu power management state diagram
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 52 - 6.4.2 power management states run the system is running normally. all clocks are running (except where gated locally). the sdram controller is performing normal refresh. slow the cpu is switched into fastbus mode (please refer to the arm720t datasheet - ddi 0087), and hence runs at the bclk rate (half the fclk rate). this is the default mode after exiting deep sleep mode or system power on. idle in this mode, the pmu becomes the bus master until there is either a fast or normal interrupt for the cpu. this will cause the clocks in the cpu to stop when it attempts an asb access. the HMS30C7210 can enter this mode by writing 0x2 to the bits [2:0] of the pmumr when in run or slow mode, or by wakeup signal activation while in sleep or deep sleep mode. note: when the cpu sets idle mode into the pmu mode register, it must read non-chachable area for enter idle state. sleep in this mode, the sdram is put into self-refresh mode, and internal clocks are gated off. this mode can only be entered from idle mode (the pmu bus master must have the mastership of the asb before this mode can be entered). the pmu must be the bus master to ensure that the system is sto pped in a safe state, and is not half way through a sdram write (for example). both the video and communication clocks (vclk and cclk) should be disabled before entering this state. usually the cpu would only drop in at this mode on the way to the deep sleep mode. deep sleep in the deep sleep mode, the crystal oscillator for the 6-mhz pll input clock and the plls are disabled. this is the lowest power state available. only the 32.768-khz rtc oscillator runs and provides clocks for the rtc logic and the debouncing logic of the pmu. everything else is powered down, and sdram is in self refresh mode. this is the normal system "off" mode. the HMS30C7210 can get out of the sleep and deep sleep modes either by a user wake-up event (generally pressing the "on" key), by an rtc wake-up alarm, or by a modem ring indicate event. these wake-up sources go directly to the pmu.
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 53 - 6.4.3 wake-up debounce and interrupt the wake-up events are debounced as follows: each of the event signals which are liable to noise ( nreset, rtc, npmwakeup, and modem ring indicator, power adapter condition ) is re-timed to a 15.625- or 250-hz clock derived from the 32.768-khz rtc clock. after being filtered to a quarter of the frequency of debouncing clock, each event has an associated `sticky' register bit. npmwakeup (active low) is an external input, which may be typically connected to an "on" key. a `sticky' bit is a register bit that is set by the incoming event, but is only reset by the cpu. thus should the fclk pll drop out of lock momentarily (for example) the cpu will be informed of the event, even if the pll has regained lock by the time the cpu can read its associated register bit. the npmwakeup, modem, real time clock, hotsync and power adapter condition inputs are combined to form the pmu interrupt. each of these four interrupt sources (except power adapter condition) can wake up the cpu form the deep sleep mode, and then the cpu can be informed of each interrupt event. all of wakeup and interrupt sources may be individually enabled. to make use of the npmwakeup interrupt, (for example) controlling software will need to complete the following tasks: ? enable the npmwakeup interrupt, by writing ?1? to bit 11 of the pmu reset / status register (pmursr). ? once an interrupt has occurred, read the pmursr register to identify the source(s) of interrupt. in the case of a npmwakeup event, the register will return 0x10. ? clear the appropriate `sticky' bit by writing a ?1? to the appropriate bit location (in the npmwakeup case, this will be the bit 4.). portb[15] (hotsync) wake-up sequence the portb[15] (hotsync) interrupt is or-gated with npmwakeup to support additional wake up sources. portb[15] (hotsync) input signal can be used as a wake up source; it is also enabled an interrupt source using the interrupt enable register of the interrupt controller. after wake up, software should program the gpio portb interrupt mask bit of the interrupt enable register and/or the hotsync interrupt mask bit of the pmursr register. one possible application is to use the ndcd signal, from the uart interface, as a wake up source, by connecting ndcd to a portb[15] input. in the deep sleep mode, ndcd can wake up the system by generating a portb[15] interrupt request to the pmu block. the pmu state machine then returns the system to the operational mode.
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 54 - 6.5 reset sequences 6.5.1 power on reset (cold reset)) npor nreset bnres vcklen, cclken (write by software) fpll, cpll lock detect vclk cclk fclk bclk pclk qclk 240us 256ms figure 6-5. a cold reset event in the removal and re-application of all power to the HMS30C7210, the following sequence may be typical: ? npor input is active. all internal registers are reset to their default values. the pmu drives nresetout low to reset any off-chip periperal devices. ? bnres becomes active on exit from npor condition. clocks are enabled temporarily to allow synchronus resets to operate. ? the default frequency of fclk on exit from npor will be 51mhz. ? when fclk is stable, the cpu clock is released. if the cpu were to read the reset / status register (pmursr) at this time, it will return 0x03e0_000d. ? the cpu may write 0x03e0_000d to the pmursr to clear these flag bits. bit meaning bit 3 set: fclk pll has been ?unlocked? bit 2 set: cclk pll has been ?unlocked? bit 0 set: power on reset event has occuerred table 6-2. bit settings for a cold reset event within pmursr register ? the cpu writes 0x0032 to the clock control register (pmuccr), which will set a fclk speed of 60mhz. the new clock frequency, however, is not adopted until the pmu has entered and left deep sleep mode.
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 55 - ? the cpu sets a rtc timer alarm to expire in approximately 2 seconds. ? the cpu sets deep sleep into the pmu mode register ? the pmu state machine will enter deep sleep mode (via the intermediate states shown in figure 6-4. pmu power management state diagram. ? when the rtc timer alarm is activated, the pmu automatically wakes up into slow mode, but with the new fclk frequency of 60mhz. ? the cpu may write 0xc032 to the clock control register, which enable cclk and vclk, and retains the new fclk frequency. nresetin nreset nreseten HMS30C7210 npor internal warm reset (active high) nporin figure 6-6. npor / nreset / softwarereset function
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 56 - 6.5.2 software generated warm reset npor nreset bnres vcklen, cclken (write by software) fpll, cpll lock detect vclk cclk fclk bclk pclk qclk 256ms reset/status warmreset figure 6-7. software generated warm reset ? the cpu writes ?1? to the warmreset bit of reset / status register. the pmu drives nreset low. the internal chip reset, bnres is drive low. the pmu detects that the bidirectional nreset pin is low. nreset is filtered by a de- bounce circuit. note that this means that nreset will remain low for a mininum of 256ms (15.625hz pulse x 4). bnres becomes active once the de-bounced nreset goes high once more, whihc disables vclk and cclk. the cpu may read the reset / status register, which will return 0x03e0_010c. bit meaning bit 8 set: warm reset event has occurred. bit 3 set: fclk pll has been ?unlocked? bit 2 set: cclk pll has been ?unlocked? table 6-3. bit settings for a software generated warm reset within reset / status register
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 57 - 6.5.3 an externally generated warm rese npor nreset bnres vcklen, cclken (write by software) fpll, cpll lock detect vclk cclk fclk bclk pclk qclk 512ms figure 6-8. an externally generated warm reset ? nreset is driven to ?0? by external hardware. the nreset input is filtered by a de-bounce circuit. note that this means that nreset must remain low for a minimum of 512ms. bnres (the on-chip reset signal) becomes active as soon as nreset is low, and high once the de-bounced nreset goes high once. bnres disables vclk and cclk. the cpu may read the reset / status register, which will return 0x03e0_010c. bit meaning bit 8 set: warm reset event has occurred. bit 3 set: fclk pll has been ?unlocked? bit 2 set: cclk pll has been ?unlocked? table 6-4. bit settings for a warm reset within reset / status register note. the internal chip reset, bnres remains active for 256ms after an externally generated nreset. external devices should not assume that the HMS30C7210 is in an active state during this period.
pmu & pll magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 58 -
sdram controller magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 59 - 7 sdram controller the sdram controller operates at the full cpu core frequency (fclk) and is connected to the core via the asb bus. internally the sdram controller arbitrates between access requests from the main amba bus, and the lcd bus. it can control up to two sdrams of 256mbit (x16) density maximum. to reduce the system power consumption it can power down these individually using the clock enable (cke). when the mcu is in standby mode the sdrams are powered down into self-refresh mode. sdrams achieve the highest throughput when accessed sequentially ? like lcd data. however accesses from the core are less regular. the sdram controller uses access predictability to maximize the memory interface bandwidth by having access to the lcd address buses. lcd accesses to the sdram occur in fixed-burst lengths of 16 words. arm accesses occur in a fixed-burst length of four words. if the requested accesses are shorter than four words, then the extra data is ignored. features ? 16 bits wide external bus interface (two access requires for each word) ? supports 16/64/128/256mbit device ? supports 2~64 mbytes in up to two devices (the size of each memory device may be different) ? programmable cas latency ? supports 2/4 banks with page lengths of 256 or 512 half words ? programmable auto refresh timer ? support low power mode when idle (each device?s cke is disable individually). asb interface (30mhz domain) sdram interface (60mhz domain) lcd interface mainbus register writebuffer mainfsm sdfsm sdbanks sdtim sdpin (60mhz feedback clock domain) amba (asb) lcd conteroller external sdram figure 7-1. sdram controller block diagram
sdram controller magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 60 - 7.1 supported memory devices 2-64mbytes of sdram are supported with any combination of one or two 16/64/128/256mbit devices. each device is mapped to a 32mbyte address space. the mmu (memory management unit) maps different device combinations (e.g. 16- and 64mbit devices) into a continuous address space for the arm core. total memory 16mbit devices 64mbit devices 128mbit devices 256mbit devices 2mbyte 1 - - - 4mbyte 2 - - - 8mbyte - 1 - - 16mbyte - 2 1 - 32mbyte - - 2 1 64mbyte - - - 2 note the HMS30C7210 can use any mixture of 16-, 64-, 128- or 256mbit sdrams. it is the responsibility of software to determine the actual external memory configuration, and to program the memory management unit appropriately. the sdram controller allows up to four memory banks to be open simultaneously. the open banks may exist in different physical sdram devices.
sdram controller magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 61 - 7.2 external signals pin name type description ra [14:11] sa10 ra [9:0] o sdram address bus rd [15:0] i/o sdram data bus sclk o sdram clock output scke [1:0] o sdram clock enable outputs nras o sdram row address select output ncas o sdram column address select output nswe o sdram write enable output nscs [1:0] o sdram chip select outputs dqml o sdram lower data byte enable dqmu o sdram upper data byte enable refer to figure 2-1. 208 pin diagram. 7.3 registers the sdram controller has three registers: the configuration, refresh timer and the write buffer flush timer. the configuration register's main function is to specify the number of sdrams connected, and whether they are 2- or 4-bank devices. the refresh timer gives the number of bclk ticks that need to be counted in-between each refresh period. the write buffer flush timer is used to set the number of bclk ticks since the last write operation, before the write buffer's contents are transferred to sdram. address name width default description 0x8000.0000 sdcon 32 0x0070 0000 configuration register 0x8000.0004 sdref 16 0x0000 0080 refresh timer 0x8000.0008 sdwbf 3 0x0000 0000 write back buffer flush timer table 7-1 sdram controller register summary in addition to the sdram control registers, the arm may access the sdram mode registers by writing to a 64mbyte address space referenced from the sdram mode register base address. writing to the sdram mode registers is discussed further..
sdram controller magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 62 - 7.3.1 sdram controller configur ation register (sdcon) 0x8000.0000 31 30 29 28 27 26 25 24 s1 s0 - - - - - - 23 22 21 20 19 18 17 16 r a c1 c0 d c b - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 e1 b1 - - e0 b0 - - bits type function 31:30 r sdram controller status, read-only s[1:0] = 11, reserved s[1:0] = 10, self refresh s[1:0] = 01, busy s[1:0] = 00, idle 23 r/w normal sdram controller refresh enable 1 = the sdram controller provides refresh control 0 = the sdram controller does not provide refresh 22 r/w auto pre-charge on asb accesses 1 = auto pre-charge (default) 0 = no auto pre-charge 21:20 r/w cas latency control c[1:0] = 11, cas latency 3 c[1:0] = 10, cas latency 2 c[1:0] = 01, cas latency 1 c[1:0] = 00, reserved 19 r/w sdram bus tri-state control 0 = the controller drives the last data onto the sdram data bus (default) 1 = the sdram bus is tri-stated except during writes this bit should be cleared before the ic enters a low power mode. driving the data lines avoids floating inputs that could increase device power consumption. during normal operation the d bit should be set, to avoid data bus drive conflicts with sdram. 18 r/w sdram clock enable control 0 = the clock of idle devices are disabled to save power (default) 1 = all clock enables are driven high continuously 17 r/w write buffer enable value = 1 if the write buffer is enabled value = 0 if the write buffer is disabled 7 r/w device enable ? indicates that there is a physical sdram present in each of the two slots in the address map. this bit is used to determine whether an auto-refresh command should be issued to a particular memory device. 1 = a device is present at address range 32-64mbyte (slot 1) 0 = a device is not present at address range 32-64mbyte 6 r/w indicates whether the sdram in the slot is a 2- or 4-bank device 1 = the sdram is a four-bank device 0 = the sdram is a two-bank device 3 r/w device enable ? indicates that there is a physical sdram present in each of the two slots in the address map. this bit is used to determine whether an auto-refresh command should be issued to a particular memory device. 1 = a device is present at address range 0-32mbyte (slot 0) 0 = a device is not present at address range 0-32mbyte 2 r/w indicates whether the sdram in the slot is a 2- or 4-bank device 1 = the sdram is a four-bank device 0 = the sdram is a two-bank device
sdram controller magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 63 - the sdram controller configuration register is a 32-bit wide split read/write register, such that bits [23:0] should be configured by the arm, and bits [31:24] provide status information that read-only. all locations containing ?-?are for future expansion, and should always be programmed with the binary value 0. writes to bits [31:24] are always ignored. during power-up initialization, it is important that the e[1:0] and the r bits are set in the correct sequence. the sdram controller powers-up with e[1:0]=00 and r=0. this indicates that the memory interface is idle. next, the software should set at least one e bit to 1 with the r bit 0. this will cause both devices to be precharged (if present). the next operation in the initialization sequence is to auto-refresh the sdrams. note that the number of refresh operations required is device-dependent. set r=1 and e[1:0]=00 to start the auto-refresh process. software will have to ensure that the prescribed number of refresh cycles is comp leted before moving on to the next step. the final step in the sequence is to set r=1 and to set the e bits corresponding to the populated slots. this will put the sdram controller (and the sdrams) in their normal operational mode. write e[1:0]=00 r=0 write e[1:0]=01 r=0 write e[1:0]=00 r=1 write e[1:0]=according to slot populated r=1 refresh complete? software example operation memory operation no,wait yes idle precharge auto refresh memory refreshing memory start normal operation end of initialization figure 7-2. sdram controller software example and memory operation diagram
sdram controller magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 64 - 7.3.2 sdram controller refresh timer register (sdref) 0x8000.0004 - 15 ? 0 reserved sdref bits type function 15:0 r/w a 16-bit read/write register that is programmed with the number of bclk ticks that should be counted between sdram refresh cycles. for example, for the common refresh period of 16us (16x10e-6), and a bclk frequency of 30mhz (30x10e6), the following value should be programmed into it: (16x10e-6) x (30x10e6) = 480 the refresh timer defaults to a value of 128, which for a 16us refresh period assumes a worst case (i.e. slowest) clock rate of: 128 / (16x10e-6) = 8 mhz the refresh register should be programmed as early as possible in the system start-up procedure, and in the first few cycles if the system clock is less than 8mhz. 7.3.3 sdram controller write buffer flush timer register (sdwbf) 0x8000.0008 - 2 ? 0 reserved sdwbf bits type function 2:0 r/w a 3-bit read/write register that sets the time-out value for flushing the quad word merging write buffer. the times are given in the following table. timer value bclk ticks between time-outs 111 128 110 64 101 32 100 16 011 8 010 4 001 2 000 time-out disabled
sdram controller magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 65 - 7.4 power-up initialization of the sdrams the sdrams are initialized by applying power, waiting a prescribed amount of settling time (typically 100us), performing at least 2 auto-refresh cycles and then writing to the sdram mode register. the exact sequence is sdram device- dependent. the settling time is referenced from when the sdram clk starts. the processor should wait for the settling time before enabling the sdram controller refreshes, by setting the r bit in the sdram control register. the sdram controller automatically provides an auto refresh cycle for every refresh period programmed into the refresh timer when the r bit is set. the processor must wait for sufficient time to allow the manufacturer's specified number of auto-re fresh cycles before writing to the sdram?s mode register. the sdram's mode register is written to via its address pins (a[14:0]). hence, when the processor wishes to write to the mode register, it should read from the binary address (amba address bits [24:9]), which gives the binary pattern on a[14:0] which is to be written. the mode register of each of the sdrams may be written to by reading from a 64mbyte address space from the sdram mode register base address. the correspondence between the amba address bits and the sdram address lines (a[14:0]) is given in the row address mapping of table 7-2 sdram row/column address map. bits [25] of the amba address bus select the device to be initialized. the sdram must be initialized to have the same cas latency as is programmed into c[1:0] bits of the sdram control register, and always to have a burst length of 8.
sdram controller magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 66 - 7.5 sdram memory map the sdram controller can interface with up to two sdrams. four sdram sizes are supported -- 16, 64, 128 and 256mbits -- which may be organized in either two or four banks but which must have a 16-bit data bus. a maximum of 64mbytes of memory may be addressed by the sdram controller, which subdivided into two 32mbyte blocks, one for each of the external sdrams. the mapping of the amba address bus to the sdram row and column addresses is given in table 7-2 sdram row/column address map. the first row of the diagram indicates the sdram address bit (a[14:0]); the remaining numbers indicate the amba address bits ba[24:1]. note that for 16mbit device, pins a[11,9] on thee sdram should be connected to pins ra[13,12] on the HMS30C7210, and the pins ra[11,9] should not be connected. sdram addr 14 13 (bs0 ) 12 (bs1 ) 11 10 9 8 7 6 5 4 3 2 1 0 row 16mbit 24 10* 9* note 1 20* note 1 19* 18* 17* 16* 15* 14* 13* 12* 11* col 16mbit 24 10 10 note 1 20 note 1 23 8* 7* 6* 5* 4* 3* 2* note 2 row 64mbit 24 10* 9* 22* 20* 21* 19* 18* 17* 16* 15* 14* 13* 12* 11* col 64mbit 24 10 10 22 20 21 23 8* 7* 6* 5* 4* 3* 2* note 2 row 128mbit 24 10* 9* 22* 20* 21* 19* 18* 18* 16* 15* 14* 13* 12* 11* col 128mbit 24 10 10 22 20 21 23* 8* 7* 6* 5* 4* 3* 2* note 2 row 256mbit 24* 10* 9* 22* 20* 21* 19* 18* 18* 16* 15* 14* 13* 12* 11* col 256mbit 24 10 10 22 20 21 23* 8* 7* 6* 5* 4* 3* 2* note 2 mode write 24* 10* 9* 22* 20* 21* 19* 18* 17* 16* 15* 14* 13* 12* 11* summar y 24 10 9 22 20 21 19/23 18/8 17/7 16/6 15/5 14/4 13/3 12/2 11* table 7-2 sdram row/column address map notes (1) for the 16mbit device, sdram address line a11 should be connected to the HMS30C7210 pin ra[13](bs0), and the sdram address line a9 should be connected to the HMS30C7210 pin ra[12](bs1). the HMS30C7210 address lines ra[11] and ra[9] should not be connected . (2) since all burst accesses commence on a word boundary, and sdram addresses are non-incrementing (the address incremented is internal to the device), column address zero will always be driven to logic `0'. * an asterisk denotes the address lines that are used by the sdram. the start address of each sdram is fixed to a 32mbyte boundary. the memory management unit will be used to map the actual banks that exist into contiguous memory as seen by the arm. bits [25] of the amba address bus select the device to be initialized, as described in table 7-3. ba25 device selected 0 device 0 1 device 1 table 7-3 sdram device selection
sdram controller magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 67 - ra[14] ra[13] ra[12] ra[11] sa10 ra[9] ra[8] . . . ra[0] rd[15:0] dqmu dqml sclk scke[0] nscs[0] nras ncas nswe HMS30C7210 sdram (256mbitx16) a12 ba0 ba1 a11 a10 a9 a8 . . . a0 dq[15:0] dqmh dqml clk cke cs# ras# cas# we# figure 7-3. 256mbitx16 (4banks) device connection ra[14] ra[13] ra[12] ra[11] sa10 ra[9] ra[8] . . . ra[0] HMS30C7210 sdram (128mbitx16) ba0 ba1 a11 a10 a9 a8 . . . a0 figure 7-4. 128mbitx16 (4banks) device connection ra[14] ra[13] ra[12] ra[11] sa10 ra[9] ra[8] . . . ra[0] HMS30C7210 sdram (64mbitx16) ba0 ba1 a10 a9 a8 . . . a0 figure 7-5. 64mbitx16 (4banks) device connection
sdram controller magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 68 - ra[14] ra[13] ra[12] ra[11] sa10 ra[9] ra[8] . . . ra[0] HMS30C7210 sdram (16mbitx16) a11 a10 a9 a8 . . . a0 figure 7-6. 16mbitx16 (2banks) device connection
sdram controller magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 69 - 7.6 amba accesses and arbitration the sdram controller bridges both the amba main and video buses. on the main bus, the sdram appears as a normal slave device. on the lcd dma bus, the sdram controller integrates the functions of the bus arbiter and address decoder. writes from the main bus may be merged in the quad word merging write buffer. a main/lcd arbiter according to the following sequence arbitrates access requests from either the main or lcd buses: ? highest priority: lcd ? middle priority: refresh request ? lowest priority: main bus peripheral (pmu, arm)--order determined by main bus arbiter. lcd sdram accesses always occur in bursts of 16 words. once a burst has started, the sdram controller provides data without wait states. lcd data is only read from sdram, no write path is supported. if a refresh cycle is requested, then it will have lower priority than the video bus, but will be higher than any other accesses from the main bus. assuming a worst-case bclk frequency of 8mhz, the maximum, worst-case latency that the arbitration scheme enforces is 11.5us before a refresh cycle can take place. this is comfortably within the 16us limit. note that the 2 external sdram devices are refreshed on 2 consecutive clock cycles to reduce the peak current demand on the power source. the arbitration of the main bus is left to the main bus arbiter. data transfers requested from the main bus always occur as a burst of eight half-word accesses to sdram. the main bus arbiter cannot break into access requests from the main bus. in the case where fewer than four words are actually requested by the main bus peripheral, the excess data from the sdram is ignored by the sdram controller in the case of read operations, or masked in the case of writes. in the case where more than four words are actually requested by the main bus peripheral, the sdram controller asserts blast to force the asb decoder to break the burst. in the case of word/half-word/byte misalignment to a quad word boundary (when any of address bits [3:0] are non-zero at the start of the transfer), blast is asserted at the next quad word boundary to force the asb decoder to break the burst. sequential half word (or byte) reads are supported and the controller asserting blast at quad word boundary. in the case of byte or half word reads, data is replicated across the whole of the asb data bus. data bus for word access: 31 23 15 7 0 d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data bus for half word access: 31 23 15 7 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data bus for byte access: 31 23 15 7 0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
sdram controller magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 70 - 7.7 merging write buffer an eight word merging write-buffer is implemented in the sdram controller to improve write performance. the write buffer can be disabled, but its operation is completely transparent to the programmer. t he eight words of the buffer are split into two quad words, the same size as all data transactions to the sdrams. the split into two quad words allows one quad word to be written to at the same time as the contents of the other are being transferred to sdram. the quad word buffer currently being written to may be accessed with non-contiguous word, half word or byte writes, which will be merged into a single quad word. the buffered quad word will be transferred to the sdram when: ? there is a write to an sdram address outside the current quad word being merged into ? there is a read to the address of the quad word being merged into ? there is a time-out on the write back timer the two quad-words that make up the write buffer operate in "ping-pong" fashion, whereby one is initially designated the buffer for writes to go into, and the other is the buffer for write backs. when one of the three events that can cause a write-back occurs, the functions of the two buffers are swapped. thus the buffer containing data to be written back becomes the buffer that is currently writing back, and the buffer that was the write-back buffer becomes the buffer being written to. active buffer empty buffer active buffer empty buffer active buffer empty buffer active buffer empty buffer 1. write address miss 2. buffer swapping 3. real writing 4. buffer flusing figure 7-7. write miss flusing in the case of a write-back initiated by a read from the same address as the data in the merge buffer, the quad word in the buffer is written to sdram, and then the read occurs from sdram. the write before read is essential, because not all of the quad word in the buffer may have been updated, so its contents need to be merged with the sdram contents to fill any gaps where the buffer was not updated. active buffer empty buffer active buffer empty buffer active buffer empty buffer from sdram 1. read address hit 2. buffer swapping 3. buffer flushing 4. read from sdram figure 7-8. read hit flusing
sdram controller magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 71 - the write buffer flush timer forces a write back to occur after a programmable amount of time. every time a write into the buffer occurs, the counter is re-loaded with the programmed time-out value, and starts to counts down. if a time-out occurs, then data in the write buffer is written to sdram. active buffer empty buffer active buffer empty buffer active buffer empty buffer 1. flushtimer timeover 2. buffer swapping 3. buffer flushing figure 7-9. timer timeover flusing
sdram controller magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 72 -
static memory interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 73 - 8 static memory interface the static memory controller interfaces the amba advanced system bus (asb) to external memory systems e,g, sram, flash, rom. it can be programmed to use ebi(external bus interface) or not. it provides four separate memory or expansion banks. each bank is 16mb in size and can be programmed individually to support: features ? unified external bus interface with sdram address and data pins ? 8- or 16-bit wide, little-endian memory ? alignment error checking ? burst read access support ? variable wait states (up to 15 for read, up to 16 for write) :: unable to write with zero wait state ? smc (nand flash memory) access support (see smc controller, section 9.8.3 smc access using ebi interface) in addition, burst mode access allows fast sequential read access by the system bus commands. this can significantly improve bus bandwidth in reading from memory (that must support at least four word burst reads).
static memory interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 74 - 8.1 external signals pin name type description nrwe[1:0] o these signals are active low write enables for each of the memory byte lanes on the external bus. nroe o active low output enable nrcs[3:0] o active low chip selects. ra [23:0] o address bus rd [15:0] i/o data bus refer to figure 2-1. 208 pin diagram. 8.2 registers address name width default description 0x8002.0004 bank0_reg 13 0x0041 memory configuration register 0 0x8002.0008 bank1_reg 13 0x0041 memory configuration register 1 0x8002.000c bank2_reg 13 0x0041 memory configuration register 2 0x8002.0010 bank3_reg 13 0x0041 memory configuration register 3 table 8-1 static memory controller register summary
static memory interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 75 - 8.2.1 mem configuration register 12 11 10 9 8 7 6 5 4 3 2 1 0 bt dne bur en burst read wait state normal access wait state - mem width bits type function 31:13 reserved 12 r/w boot done this controller can have the boot bits which defines the memory size for the booting. and in the boot mood, all external memory bank memory size is determined only by the boot bits signal. so, when the booting is done, attached external memory size should be properly set by the host software. *** mem width field can only be set when this bit is logic 1. so, after booting is done, the host software should set this bit to logic 1 for properly setting the attached memory size. 11 r/w burst enable setting this bit enables burst reads to take advantage of faster access times from memory devices that support burst mode. 10:7 r/w burst read wait state value number of burst read wait state :: same as the bit number 0000 0 0001 1 ?? 1111 15 default wait is not set 6:3 r/w normal access wait state value number of normal access wait state 0000 0(read mode), 1(write mode) 0001 1(read mode), 2(write mode) ?? 1111 15(read mode), 16(write mode) default is 1000 (8, read mode :: 9, write mode) :: in case of read operation, the asserted wait numbers are equal to the value of this field. but, in write operation, the asserted wait number should add 1 to this field value. so, write operation to external memory can?t be done in zero wait 2 - - 1:0 r/w memory width 00 :: 8bit-wide memory 01 :: 16bit-wide memory 10 :: reserved 11 :: reserved for future use
static memory interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 76 - 8.3 functional description the static memory controller (smi) has six main functions: ? memory bank select ? access sequencing ? wait states generation ? burst read control ? byte lane write control these are described below 8.3.1 memory bank select internally, the static memory controller can support up to four external memory bank and for this purpose, it?s equipped with four bank controller registers. but externally, only one chip select pin is assigned. so, only bank0 can be used for external memory access. case i. romswap is ?1? address mapping (means that external booting) start address address (hex) size description (256m +0m)byte 0x0000.0000 16mbytes rom chip select 0 (256m+ 16m)byte 0x0100.0000 16mbytes rom chip select 1 (256m + 32m)byte 0x0200.0000 16mbytes rom chip select 2 (256m + 64m)byte 0x0300.0000 16mbytes rom chip select 3 case ii. romswap is ?0? address mapping (means that internal booting) start address address (hex) size description (256m +0m)byte 0x1000.0000 16mbytes rom chip select 0 (256m+ 16m)byte 0x0100.0000 16mbytes rom chip select 1 (256m + 32m)byte 0x0200.0000 16mbytes rom chip select 2 (256m + 64m)byte 0x0300.0000 16mbytes rom chip select 3 refer to figure 4-1, figure 4-2. 8.3.2 access sequencing bank configuration also determines the width of the external memory devices. when the external memory bus is narrower than the transfer initiated from the current master, the internal transfer will take several external bus transfers to complete. and in addition, the access to external memory should always meet the alignment condition. when there is an access which does not meet the alignment, this controller generates bus error condition which may be used for abort condition. 8.3.3 wait states generation the static memory controller supports various wait states for read and write accesses. this is configurable between zero and 15 wait states for standard memory access (write operation to external memory can?t be done in 0 wait). 8.3.4 burst read control this supports sequential access burst reads in 8- or 16-bit memories according to the abma bus signal.
static memory interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 77 - 8.3.5 byte lane write control this controls nrwe[1:0] according to transfer width, ba[1:0] and the access sequencing. the table below shows nrwe[1:0] coding case by little endian accessing to 16, 8-bit external memory bus. case 1. access : write, 16-bit external bus bsize [1:0] ba [1:0] ia [1:0] *note1 nrwe [1:0] 10 (word) xx 1x 00 xx 0x 00 01 (half) 1x 1x 00 0x 0x 00 00 (byte) 11 1x 01 10 1x 10 01 0x 01 00 0x 10 case 1. access : write, 8-bit external bus bsize [1:0] ba [1:0] ia [1:0] *note1 nrwe [1:0] 10 (word) xx 11 10 xx 10 10 xx 01 10 xx 00 10 01 (half) 1x 11 10 1x 10 10 0x 01 10 0x 00 10 00 (byte) 11 11 10 10 10 10 01 01 10 00 00 10 note1 : ia[1:0] (internal smi address)
static memory interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 78 - the write operation can be attempted with 8 or 16bit wide regardless of the attached external memory size. the translation is done internally in this controller. internally, this controller support 2bit wide write enable strobe, each for individual byte. but there exist only one external write enable strobe(nrwe[1:0]). byte size half word size word size 1 st bus cycle 2 nd bus cycle even address odd address lower byte upper byte lower byte upper byte lower byte upper byte lower byte upper byte figure 8-1. data flow at 16-bit width memory byte size half word size word size 1 st bus cycle 2 nd bus cycle 1 st bus cycle 2 nd bus cycle 3 rd bus cycle 4 th bus cycle lower byte lower byte lower byte lower byte lower byte lower byte lower byte figure 8-2. data flow at 8-bit width memory
static memory interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 79 - nrwe[0] nrwe[1] nrd nce noe nwe io[7:0 ] [7:0] [15:8] rd nce noe nwe io[7:0] ncs figure 8-3. 16-bit bank configuration with 8-bit width memory rd[7:0] nce noe nwe io[7:0] ncs nrd nrwe[0] figure 8-4. 8-bit bank configuration with 8-bit width memory nrwe[0] rd[15:0] nrd ncs nce noe nwe nub nlb io[15:0] figure 8-5. 16-bit bank configuration with 16-bit width memory
static memory interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 80 - 8.4 read, write timing diagram for external memory 8.4.1 read access timing (single mode) bclk /rcs /roe n ra n+1 n+2 n+3 trec tsu(a) tsu(ce0) tho(a) rd tsu(d) tho(d) tho(ce0) t figure 8-1 read access timing (single mode) name description min typical unit note tsu(a) address to /roe falling-edge setup time 30 tho(a) /roe rising-edge to address hold time 0 tsu(ce0) /rcs falling-edge to /roe falling-edge setup time 30 tho(ce0) /roe rising-edge to /rcs rising-edge setup time -15 trec /roe negate to start of next cycle 30 tsu(d) data setup time before latch 5 tho(d) data hold time after latch 0 ns table 8-2. timing values for read access in single mode data transfer (bclk=33mhz)
static memory interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 81 - 8.4.2 read access timing (burst mode) bclk /rcs /roe n ra n+1 n+2 n+3 rd tsu( a ) tsu(ce0) tsu(ce1) tho(a) tsu(d) tho(d) tho(ce1) figure 8-2 read access timing (burst mode) name description min typical unit note tsu(a) address to /roe falling-edge setup time 15 tho(a) /roe rising-edge to address hold time -15 tsu(ce0) /rcs falling-edge to /roe falling-edge setup time 15 tho(ce0) /roe rising-edge to /rcs rising-edge setup time -15 tho(ce1) /roe or /rwe rising-edge to /rcs falling-edge hold time 45 tsu(ce1) /rce rising-edge to /roe or /rwe falling-edge setup time 75 tsu(d) data setup time before latch 5 tho(d) data hold time after latch 0 ns table 8-3. timing values for read access in burst mode data transfer (bclk=33mhz)
static memory interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 82 - 8.4.3 write access timing bclk /rcs /rwe n ra n+1 n+2 n+3 rd trec(wr) tsu(a) tsu(ce0) tho(a) tloz(d) tacc thiz(d) tho(ce0) figure 8-3 write access timing name description min typical unit note tsu(a) address to /rwe falling-edge setup time 15 tho(a) /rwe rising-edge to address hold time 15 tsu(ce0) /rcs falling-edge to /rwe falling-edge setup time 15 tho(ce0) /rwe rising-edge to /rcs rising-edge setup time 15 trec(wr) /rwe negate to start of next cycle 30 thiz(d) /rwe rising edge to d hi-z delay 30 tloz(d) /rwe falling-edge to d driven 0 ns table 8-4. timing values for write access (bclk=33mhz)
amba peripherals magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 83 - 9 amba peripherals this chapter describes the peripherals that are connected to the 3.692308mhz internal peripheral bus; these are peripherals that need relatively low data rates on the internal bus. (call apb)
amba peripherals magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 84 -
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 85 - 9.1 lcd controller features ? single panel color and monochrome stn displays ? resolution programmable up to 640x480 ? single panel stn displays with either 4- or 8-bit interfaces ? 8 and 12 bits per pixel for color display ? 1, 2, and 4 bits per pixel for monochrome display ? big and little endian pixel order in a byte. ? palette for 256 colors and 15 gray-level monochrome ? programmable timing for various display panels ? patented grayscale algorithm ? relocatable frame buffer for internal sram and sdram note. the controller does not support dual panel stn displays. there is no hardware cursor support, since wince does not use a cursor. internal sram sdram fifo palette gray scaler lcd timing generator apb interface lcp lfp llp lac ld[7:0] lcd data formatter system bus: apb bclk vclk dma lcd controller to lcd panel lcden lblen figure 9-1. block digram of lcd controller
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 86 - 9.1.1 external signals pin name type description lcden o power on/off signal for a lcd panel lblen o backlight enable signal for a lcd panel lfp o lcd frame pulse (corresponds to frame pin of a lcd panel) llp o lcd line pulse (corresponds to cl1 pin of a lcd panel) lcp o lcd clock pulse (corresponds to cl2 pin of a lcd panel) lac o lcd ac bias ld[7:0] o lcd data bus refer to figure 2-1. 208 pin diagram. 9.1.2 registers address name width default description 0x8005.2000 lcdcontrol 16 0000.0000 lcd control register 0x8005.2004 lcdstatus 4 0000.0000 lcd status register 0x8005.2008 lcdstatusm 4 0000.0000 lcd status mask register 0x8005.200c lcdinterrupt 4 0000.0000 lcd interrupt register 0x8005.2010 lcddbar 32 0000.0000 lcd dma channel base address register 0x8005.2014 lcddcar 32 0000.0000 lcd dma channel current address register 0x8005.2020 lcdtiming0 32 0000.0000 lcd timing 0 register 0x8005.2024 lcdtiming1 32 0000.0000 lcd timing 1 register 0x8005.2028 lcdtiming2 32 0000.0000 lcd timing 2 register 0x8005.2030 lcdpaletter 32 7654.3210 lcd palette for red color or lsp 0x8005.2034 lcdpaletteg 32 fedc.ba98 lcd palette for green color or msp 0x8005.2038 lcdpaletteb 16 0000.fa50 lcd palette for blue color table 9-1. lcd controller register summary
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 87 - 9.1.2.1 lcd control register (lcdcontrol) 0x80052000 13 12 10 9 8 vcomp lep bpp 6 5 4 2 1 0 bgr ldw bw blen pwren lcden bits type function 31:14 - reserved 13:12 r/w vcmode (vertical compare mode) generate interrupt at: 00 - start of vsync 01 - start of back porch 10 - start of active video 11 - start of front porch 11 - reserved 10 r/w lep (little endian pixel) 0 - big endian pixel order in a byte 1 - little endian pixel order in a byte 9:8 r/w bpp (bits per pixel) 00 - 1bpp 01 - 2bpp 10 - 4bpp 11 - 8bpp (for color display only) 7 - reserved 6 r/w bgr (blue-green-red mode for color mode) 0 - rgb normal video output for lcd 1 - bgr red and blue swapped for lcd 5 r/w ldw (lcd data bus width for monochrome mode) 0 - 4-bit data width lcd module 1 - 8-bit data width lcd module 4 r/w bw (monochrome or color display mode) 0 - color operation enabled 1 - monochrome operation enabled 3 - reserved 2 r/w blen (lcd backlight enable) this drives "0" or "1" out to the lcd backlight enable pin 1 r/w pwren (lcd power enable) 0 - lcd is off 1 - lcd is on when lcden=1 0 r/w lcden (lcd controller enable) 0 - lcd controller disabled 1 - lcd controller enabled
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 88 - 9.1.2.2 lcd controller status/mask and interrupt registers (lcdstatus, lcdstatusm, and lcdinterrupt) 0x80052004 ~ 0x8005200c 3 2 1 0 ldone vcomp lnext lfuf bits type function 31:4 - reserved 3 r ldone (lcd done frame status/mask/interrupt bit) the lcd frame done (done) is a read-only status bit that is set after the lcd has been disabled (lcden = 0) and the frame that is current active finishes being output to the lcd's data pins. it is cleared by writing the base address (lcddbar) or enabling the lcd, or, by writing "1" to the ldone bit of the status register. when the lcd is disabled by clearing the lcd enable bit (lcden=0) in lcdcontrol, the lcd allows the current frame to complete before it is disabled. after the last set of pixels is clocked out onto the lcd's data pins by the pixel clock, the lcd is disabled and done is set. 2 r/w vcomp (vertical compare status/mask/interrupt bit) this bit is set when the lcd timing generator reaches the vertical region, vcomp, programmed in the video control register. this bit is "sticky", meaning it remains set until it is cleared by writing a "1" to this bit 1 r lnext (lcd next base address update status/mask/interrupt bit) the lcd next frame (lnext) is a read-only status bit that is set after the contents of the lcd dma base address register are transferred to the lcd dma current address register at the start of frame, and it is cleared when the lcd dma base address register is written. 0 r/w lfuf (fifo underflow status/mask/interrupt bit) the lcd fifo underflow (lfuf) status bit is set when the lcd fifo unde r-runs. the status bit is "sticky", meaning it remains set after the fifo is no longer underrunning. the status bit is cleared by writing a `1' to this bit.
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 89 - 9.1.2.3 lcd dma base address register (lcddbar) 0x80052010 31 30 29 28 27 26 25 24 23 22 21 20 29 28 17 16 0 lcddbar 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lcddbar (continued) 0 0 0 0 0 0 bits type function 31 - reserved. keep these bits zero 30:6 r/w lcd dma channel base address pointer 16-word aligned base address of the frame buffer (sdram or internal sram) 5:0 - reserved. keep these bits zero 9.1.2.4 lcd dma channel current address register (lcddcar) 0x80052014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 lcddcar 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lcddcar (continued) 0 0 0 0 0 0 bits type function 31 - read as zero 30:6 r lcd dma channel current address pointer 16-word aligned current address pointer to data in frame buffer currently being displayed 5:0 - read as zero
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 90 - 9.1.2.5 lcd timing 0 register (lcdtiming0) 0x80052020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 hbp hfp 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 hsw ppl bits type function 31:24 r/w hbp (horizontal back porch) the 8-bit hbp field is used to specify the number of pixel clock periods to insert at the beginning of each line or row of pixels. after the line clock for the previous line has been negated, the value in hbp is used to count the number of pixel clocks to wait before starting to output the first set of pixels in the next line. hbp generates a wait period ranging from 1-256 pixel clock cycles (number of lclk clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display minus 1). hbp = # of lclk ? 1 23:16 r/w hfp (horizontal front porch) the 8-bit hfp field is used to specify the number of pixel clock periods to insert at the end of each line or row of pixels before pulsing the line clock pin. once a complete line of pixels is transmitted to the lcd driver, the value in hfp is used to count the number of pixel clocks to wait before pulsing the line clock. hfp generates a wait period ranging from 1-256 pixel clock cycles. (program to value required minus 1). hfp = # of lclk ? 1 15:8 r/w hsw (horizontal sync pulse width) the 8-bit hsw field is used to specify the pulse width of the line clock. number of lclk clock periods to pulse the line clock at the end of each line minus 1 hsw = # of lclk ? 1 7 - reserved 6:0 r/w ppl (pixels per line) ppl is used to specify the number of pixels in each line or row on the screen. ppl is a 7-bit value that represents between 16-2048 pixels per line. ppl is used to count the correct number of pixel clocks that must occur before the line clock can be pulsed. program the value required divided by 16, minus 1. ppl = ( actual_pixels_per_line / 16 ) ? 1
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 91 - 9.1.2.6 lcd timing 1 register (lcdtiming1) 0x80052024 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 vsw lps bits type function 31:16 r/w reserved. keep these bits zero 15:10 r/w vsw (vertical sync pulse width) the 6-bit vsw field is used to add extra dummy line clock delays between frames. the value should be small for stn lcd, but should be long enough to re-program the video palette under interrupt control, without writing the video palette at the same time as video is being displayed. the register is programmed with the number of lines of vsync minus 1. vsw = # of lines ? 1 9:0 r/w lps (lines per screen) the lps bit-field is used to specify the number of lines or rows per lcd panel being controlled. lps is a 10-bit value that represents 1-1024 lines per screen. the register is programmed with the number of lines per screen minus 1. lps = actual_lines_per_screen ? 1
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 92 - 9.1.2.7 lcd timing 2 register (lcdtiming2) 0x80052028 31 30 29 28 24 23 22 21 20 17 16 iac icp ilp ifp acb cpl 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cpl (continued) lcs csd pcd bits type function 31 r/w iac (invert lac pin) the iac bit is used to invert the polarity of the lac signal. 0 - lac pin is active high and inactive low 1 - lac pin is active low and inactive high 30 r/w icp (invert lcp pin) the icp bit is used to select which edge of the pixel clock pixel data is driven out onto the lcd's data lines. when ipc=0, data is driven onto the lcd's data lines on the rising-edge of lcp. when ipc=1, data is driven onto the lcd's data lines on the falling-edge of lcp. 0 - data is driven on the lcd's data lines on the rising-edge of lcp. 1 - data is driven on the lcd's data lines on the falling-edge of lcp. 29 r/w ilp (invert llp pin) the ilp bit is used to invert the polarity of the llp signal. 0 - llp pin is active high and inactive low. 1 - llp pin is active low and inactive high. 28 r/w ifp (invert lfp pin) the ifp bit is used to invert the polarity of the lfp signal. 0 - lfp pin is active high and inactive low. 1 - lfp pin is active low and inactive high. 27:25 - reserved 24:20 r/w acb (ac bias pin frequency) the 5-bit acb field is used to specify the number of line clock periods to count between each toggle of the ac-bias pin (lac). this pin is used to periodically invert the polarity of the power supply to prevent dc charge build-up within the display. the value programmed is the number of lines between transitions, minus 1. acb = # of lines ? 1 19:18 - reserved 17:8 r/w cpl (clocks per line) this is the actual number of clocks output to the lcd panel each line, minus 1. this must be programmed, in addition to the ppl field in the lcd timing 0 register. the number of clocks per line is the number of pixels per line divided by 4, 8 or two-and-two-thirds for mono 4-bit mode, mono 8-bit, or color stn mode (2 ? ) respectively. cpl = actual_clocks_per_line ? 1 7 r/w lcs (lcd clock source selection) 0 - system bus clock (bclk) 1 - video clock from pmu (vclk) 6:5 r/w csd (lcd clock source divisor) the selected clock by lcs bit is divided by lcd pre-divider. the divided source clock becomes the fundamental clock of lcd controller, lclk. 00 ? no division 01 ? clock is divided by 4 10 ? clock is divided by 16 11 ? reserved 4:0 r/w pcd (pixel clock divisor) pcd is used to specify the frequency of lcp signal based on lclk frequency. pixel clock frequency can range from lclk/2 to lclk/33, where lclk is the clock divided by csd. f lcp = f lclk / ( pcd + 2 ) note that f lcp is not the frequency of some nominal clock rate that individual pixels are output to the lcd. in normal mono mode (4-bit interface), four pixels are output per lcp cycle, so the pixelclock is one quarter the nominal pixel rate. in the case of 8-bit interface, pixelclock is one-eighth the nominal pixel rate, since 8 pixels are output per lcp cycle. in the case of color, pixelclock is 0.375 times the nominal pixel rate, because 2 ? pixels are output per lcp cycle.
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 93 - 9.1.2.8 lcd palette registers (lcdpaletter, lcdpaletteg, lcdpaletteb, lcdpalettelsp, and lcdpalettemsp) 0x80052030 lcdpaletter (lcdpalettelsp for monochrome display) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 palette value for pixel value 7 palette value for pixel value 6 palette value for pixel value 5 palette value for pixel value 4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 palette value for pixel value 3 palette value for pixel value 2 palette value for pixel value 1 palette value for pixel value 0 0x80052034 lcdpaletteg (lcdpalettemsp for monochrome display) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 palette value for pixel value 7 or pixel value 15 for mono disp palette value for pixel value 6 or pixel value 14 for mono disp palette value for pixel value 5 or pixel value 13 for mono disp palette value for pixel value 4 or pixel value 12 for mono disp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 palette value for pixel value 3 or pixel value 11 for mono disp palette value for pixel value 2 or pixel value 10 for mono disp palette value for pixel value 1 or pixel value 9 for mono disp palette value for pixel value 0 or pixel value 8 for mono disp 0x80052038 lcdpaletteb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 palette value for pixel value 3 palette value for pixel value 2 palette value for pixel value 1 palette value for pixel value 0
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 94 - 9.1.3 lcd controller datapath user can use both internal sram and sdram for storage of lcd frame data. the base address of frame data (lcddbar) can be located in the internal sram as well as sdram. if the size of frame data is larger than that of the internal sram, the rest of data must be stored in the head of sdram. however, user does not have to care about it, because the head of sdram is seamlessly connected to the tail of the internal sram (refer to memory map). dma of lcd controller will switch between both areas and get proper frame data from them. fifo is designed to store 32 words. if user chooses 1 bpp mode for pixel data width, fifo can store 1024 pixel data at a time. one dma operation will fill fifo with 16 words of frame data. the frame data coming out from fifo will be divided into each pixel or each color component for color mode. then it is translated by palette registers. the translated pixel or color value has 4-bit width, no matter which bpp mode user chooses. gray scaler block convert these 4 bit gun data in a single bit per gun, using a patented time/space dither algorithm. the output of the gray scaler is fed to the lcd data formatter, which formats the pixels in the correct order for the lcd panel type in use: 4 or 8 mono pixels per clock for mono panels, or 2 ? pixels per clock for color data. the output of the formatter in color mode is bursty, due to the 2 ? pixels per clock that are output, so the formatter output goes to a small fifo, which smoothes out this burstiness, before data is output to the lcd panel at a constant rate.
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 95 - 9.1.4 color/grayscale dithering entries selected from the look-up palette are sent to the color/grayscale space/time base dither generator. each 4-bit value is used to select one of 15 intensity levels. note that two of the 16 dither values are identical. the table below assumes that a pixel data input to the lcd panel is active high. that is, a ?1? in the pixel data stream will turn the pixel on, and a ?0' will turn it off. if this is not the case, the intensity order will be reversed, with "0000" being the most intense color. this polarity is lcd panel dependent. the gray/color intensity is controlled by turning individual pixels on and off at varying periodic rates. more intense grays/colors are produced by making the average time that the pixel is off longer than the average time that it is on. the proprietary dither algorithm is optimized to provide a range of intensity values that match the eye's visual perception of color/gray gradations, with smaller changes in intensity nearer to the mid-gray level, and greater nearer the black and the white levels. in color mode, red, green and blue components are gray-scaled simultaneously as if they were mono pixels. the duty cycle and resultant intensity level for all 15 color/grayscale levels is summarized in table 9-1: color/grayscale intensities and modulation rates. dither value (4 bit value from palette) intensity (0% is white) modulation rate (ration of on to on+off pixels) 1111 100.0 1 1110 100.0 1 1101 88.9 8/9 1100 80.0 4/5 1011 73.3 11/15 1010 66.6 6/9 1001 60.0 3/5 1000 55.6 5/9 0111 50.0 1/2 0110 44.4 4/9 0101 40.0 2/5 0100 33.3 3/9 0011 26.7 4/15 0010 20.0 1/5 0001 11.1 1/9 0000 0.0 0 table 9-2. lcd color/grayscale intensities and modulation rates
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 96 - 9.1.5 lcd panel dependent settings these registers need to be set carefully according to a lcd panel specification. ? bw : monochrome or color display ? bgr : rgb or bgr for color display ? ldw : lcd data bus width ? ifp, ilp, icp, iac : signal polarity ? ppl, cpl, lps : resolution ? lcs, csd, pcd : fundamental clock ? vfp, vbp, vsw, hfp, hbp, hsw, acb : control timing ? pwren, ble : lcd panel on/off control if a lcd panel is monochome, set bw as 1. for a color lcd panel, set bw as 0. in the case of a color lcd panel, the sequence of color components in a pixel can differ by product. most panels have red as the first color components of a pixel and blue as the last one. in this case, set bgr as 0. if bgr is set as 1, lcd controller displays a blue component in the first and green and red in a row. hence, you can display a image without changing the original data to a lcd panel with the different color sequence.
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 97 - lcd controller supports 8-bit data bus for a color lcd panel. however, for a mono lcd panel, 4-bit and 8-bit data bus are possible. if you set ldw as 0, lcd controller displays pixels through ld[3:0]. set ldw as 1 to display though ld[7:0]. the pixel display sequence is depicted in figure 9-2. the first pixel is output to the msb of ld. in the color display mode, the first color component is displayed in the first. ld[7] ld[6] ld[5] ld[0] ld[4] ld[3] ld[2] ld[1] ld[7] ld[6] ld[5] ld[0] ld[3] ld[2] ld[1] ld[0] ld[3] ld[2] ld[1] ld[3] ld[2] ld[1] mono lcd panel with 8-bit data bus mono lcd panel with 4-bit data bus ld[7] b ld[6] g ld[5] r ld[0] g ld[4] b ld[3] g ld[2] r ld[1] b ld[7] r ld[6] b ld[5] g color lcd panel (bg r = 1) ld[7] r ld[6] g ld[5] b ld[0] g ld[4] r ld[3] g ld[2] b ld[1] r ld[7] b ld[6] r ld[5] g color lcd panel (bg r = 0) figure 9-2. pixel display sequence of ld bus
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 98 - the lcd panel signals, lfp, llp, lcp, lac, ld, lcden, and lblen, are active high. hence, the timing diagrams for the signals are shown as active high signals. however, some lcd panels have active low signals. to display images in such panels without any glue logics, lcd controller can program a polarity of each signal. if set ifp as 1, lfp pin becomes active low and it is driven low at the start of a new frame. ilp , icp , and iac work likewise. it is depicted in figure 9-3. icp can be used to adjust timing of the lcd panel signals. lcd controller drives the signals at the rising edge of lcp when icp = 0 . it is to stable the signals at the falling edge of lcp because of most lcd panels read the signals at that time. however, if the timing of lcd panel signals is changed by glue logics such as a voltage level shifter or a lcd panel read the signals at the rising edge of lcp, you can use icp to ensure the timing margin for such cases. the lcd panel signals are driven at the falling edge of lcp when set icp as 1. lcp lfp llp lac ld[7:0] invert invert invert invert figure 9-3. changing polarity of lcd panel signals
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 99 - ppl is to set the number of pixels in each line. ppl = ( actual_pixels_per_line / 16 ) - 1 cpl is to set the number of clocks in each line. it is different to ppl because stn lcd panels display several pixels for a clock. cpl can be calculated as follows: bw = 0 (mono) bw = 1 (color) ldw = 0 (4-bit data bus) ( actual_pixels_per_line / 4 ) - 1 - ldw = 1 (8-bit data bus) ( actual_pixels_per_line / 8 ) - 1 ( actual_pixels_per_line x 3 / 8 ) - 1 lps is to set the numer of lines per screen. lps = actual_lines_per_screen - 1 bclk vclk lcs pre-divider lclk csd figure 9-4. block diagram of clock source generation lcd controller can have two different clock sources to generate lcd panel signals. if you want to use system bus clock, bclk, set lcs as 0. vclk also can be used which is generated in pmu. in this case, set lcd as 1. before the selected clock source is used in lcd controller, it is divided by csd . after the division, lclk is the fundamental clock that is used to generated lcd panel signals. the frequency of lclk is as follows: lcs = 0 (bclk) lcs = 1 (vclk) cpd = 00 (no division) f bclk f vclk cpd = 01 (1/4 division) f bclk / 4 f vclk / 4 cpd = 10 (1/16 division) f bclk / 16 f vclk / 16 cpd = 11 (reserved) unknown unknown
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 100 - pcd is to set the frequence of lcp. f lcp = f lclk / ( pcd + 2 ) hence, the period of lcp is ( pcd + 2) times to the period of lclk. t lcp = t lclk x ( pcd + 2 ) to ensure proper operation of lcd controller, there is lower bound value of pcd. bw = 0 (mono) bw = 1 (color) ldw = 0 (4-bit data bus) pcd >= 2 - ldw = 1 (8-bit data bus) pcd >= 6 pcd >= 2 llp lcp ld pcd + 2 hfp + 1 hsw + 1 hbp + 1 hfp + 1 one line (cpl + 1) x (pcd + 2) figure 9-5. timing diagram of a line with llp, lcp, and ld signals figure 9-5 shows the timing diagram of a line displayed by lcd controller. the unit of dimension is the period of lclk. pcd controls lcp signal as explained above. and hfp , hsw , and hbp control llp signal. the period and frequence of a line can be calculated: t line = ( t lcp x ( cpl + 1 ) ) + ( t lclk x ( hfp + 1 + hsw + 1 + hbp + 1 ) ) = t lclk x ( ( cpl + 1 ) x ( pcd + 2 ) + ( hfp + 1 + hsw + 1 + hbp + 1 ) ) f line = f lclk / ( ( cpl + 1 ) x ( pcd + 2 ) + ( hfp + 1 + hsw + 1 + hbp + 1 ) )
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 101 - lfp llp lcp ld line (lps+1) line 1 line 2 vsw + 1 new frame starts the first line the second line the last line figure 9-6. timing diagram of lfp signal figure 9-6 shows the timing diagram of lfp signals that is controlled by vsw . the unit of dimension is the period of a line. lcp and ld signal are drawn as simplified. every new frame starts with active lfp. the period and frequence of a frame are: t frame = t line x ( lps + 1 + vsw + 1 ) = t lclk x { ( ( cpl + 1 ) x ( pcd + 2 ) + ( hfp + 1 + hsw + 1 + hbp + 1 ) ) x ( lps + 1 + vsw + 1 ) } f frame = f line / ( lps + 1 + vsw + 1 ) = f lclk / { ( ( cpl + 1 ) x ( pcd + 2 ) + ( hfp + 1 + hsw + 1 + hbp + 1 ) ) x ( lps + 1 + vsw + 1 ) }
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 102 - lfp llp lac (acb=0) first line lcp ld 1 lac (acb=1) first line 2 3 4 lps + 1 one frame acb + 1 lps + 1 vsw + 1 acb + 1 figure 9-7. timing diagram of a frame be different by the differ figure 9-7 depicts the complete waveform of a frame. the unit of dimension is the period of a line. you can choose acb to toggle the bias level of a lcd panel. if a lcd panel uses lac pin, the value must be carefully determined to ensure the average bias level of lac as 0. if the average bias is not 0, the lcd panel may suffer long-term damage. to avoid this, the total line number, ( lps + 1 + vsw + 1), should not be the integer multiple propotion of 2 x ( acb + 1).
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 103 - 9.1.6 frame data dependent settings ? lcddbar : frame memory address ? bpp : bits per pixel ? lep : endian mode in a byte ? lcdpaletter, lcdpaletteg, lcdpaletteb, lcdpalettemsp, lcdpalettelsp : palette data the lcd dma base address register ( lcddbar ) is a read/write register used to specify the base address of the off-chip frame buffer for the lcd. addresses programmed in the base address register must be aligned on sixteen-word boundaries, thus the least significant six bits ( lcddbar [5:0]) must always be written with zeros. 31 bits of the register, including the ls 6 bits which must be zero, are valid, because lcd dma is allowed from sdram and the internal sram. the most significant bit of lcddbar is assumed as ?0?. user must initialize the base address regist er before enabling the lcd, and may also write a new value to it while the lcd is enabled to allow a new frame buffer to be used for the next frame. the user can change the state of lcddbar while the lcd controller is active, after the next frame status bit ( lnext ) is set within the lcd's status register that generates an interrupt request. this status bit indicates that the value in the base address pointer has been transferred to the current address pointer register and that it is safe to write a new base address value. this allows double- buffered video to be implemented if required. the lcd palette registers are a set of two word and one half-word registers that allow the lcd to be programmed. these registers are used for both color and monochrome display. the format of the palette data is shown below. in the color display mode, lcdpaletter register translates pixel values for red color component. lcdpaletteg and lcdpaletteb translate for green and blue color component, respectively. for 8 bpp pixel data, each color component will be unpacked from one byte, as shown below. for 1, 2, and 4 bpp, color components will not be distinguished and whole pixel data will be translated by each palette register. red green blue bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 in the monochrome display mode, lcdpaletter ( lcdpalettelsp ) is used for 8 least significant pixel values and lcdpaletteg ( lcdpalettemsp ) for 8 most significant pixel values. it is because maximum 16 palette values are required to translate pixel values in a mono 4 bpp mode. for an example, if a pixel represents 11 in the 4 bpp mode, it will be translated to the value of lcdpalettemsp [15:12]. for 1 and 2 bpp pixel data, lcdpalettemsp and a part of lcdpalettelsp which have no correspondences will be ignored. in the monochrome display mode, lcdpaletteb does nothing.
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 104 - HMS30C7210 is basically little endian. lcd frame data also follows little endian. however, user can choose the alignment of pixel data in a byte. figure 9-8 shows display order against the pixel alignment chosen by lep . for 1 and 4 bpp mode, the pixel alignment also follows the same manner as depicted in figure 9-8. pixel 0 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 bit 0 pixel 0 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 address + 0 address + 1 lcd display frame memory for lep = 1 (little endian pixel order) pixel 0 pixel 1 pixel 2 pixel 3 pixel 4 pixel 5 pixel 6 pixel 7 address + 0 address + 1 frame memory for lep = 0 (big endian pixel order) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 pixel 8 pixel 8 address + 2 address + 2 figure 9-8. pixel display order for big and little-endian pixel alignment in 2-bpp mode
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 105 - 9.1.7 other settings ? blen, pwren, lcden : enable sequence ? lcdstatus, lcdstatusm, lcdinterrupt : interrupt mode lcd panels require that the lcd controller is running before power is applied. for this reason, the lcd's power on control is not set to "1" unless both lcden and pwren are set to "1". note that most lcd displays require the lcden must be set to "1" approximately 20ms before pwren is set to "1" for powering up. likewise, pwren is set to "0" 20ms before lcden is set to "0" for powering down. to change the value of this register, lcd controller must be disabled. otherwise, lcd may display improperly. right after disabling the controller by setting lcden to ?0?, however, it may still operate until the end of displaying the current active frame. user has to refer ldone bit in lcdstatus register to ensure that lcd controller stops the operation. the lcd controller status, lcdstatus , mask, lcdstatusm , and interrupt registers, lcdinterrupt , all have the same format. each bit of the status register is a status bit that may generate an interrupt. the corresponding bits in the mask register mask the interrupt. the interrupt register is the logical and of the status and mask registers, and the interrupt output from the lcd controller is the logical or of the bits within the interrupt register. the lcd controller status register contains bits that signal an under-run error for the fifo, the dma next base update ready status, and the dma done status. each of these hardware-detected events can generate an interrupt request to the interrupt controller.
amba peripherals (lcd controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 106 -
amba peripherals (interrupt controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 107 - 9.2 interrupt controller the interrupt controller has the following features ? a status register ? selection of the output path (irq or fiq for each input) ? enabling the interrupt the interrupt controller provides a simple software interface to the interrupt system. in an arm system, two levels of interrupt are available: ? fiq (fast interrupt request) for fast, low-latency interrupt handling ? irq (interrupt request) for more general interrupts ideally, in an arm system, only a single fiq source would be in use at any particular time. this provides a true low-latency interrupt, because a single source ensures that the interrupt service routine may be executed directly without the need to determine the source of the interrupt. it also reduces the interrupt latency because the extra- banked registers, which are available for fiq interrupts, may be used to maximum efficiency by preventing the need for a context save. the interrupt controller provides a bit position for each different interrupt source. bit positions are defined for a software-programmed interrupt. any interrupt source can be programmed as a source to fiq or irq in terrupt. all interrupt source inputs must be active high and level sensitive. neither hardware priority scheme nor any form of interrupt vectoring is provided, because these functions can be provided in software. any interrupt source may be masked.
amba peripherals (interrupt controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 108 - 9.2.1 registers address name width default description 0x8005.0000 enable 29 0x0000000 interrupt enable register 0x8005.0004 dir 29 0x0000000 interrupt direction register 0x8005.0008 status 29 0x0000000 interrupt status register 0x8005.000c - 0 0x000000 reserved for test only : do not write 0x8005.0010 0 0x000000 reserved for test only : do not write 0x8005.0020 irqfiq 2 0x3 irq/fiq status register table 9-3. interrupt controller register summary
amba peripherals (interrupt controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 109 - 9.2.1.1 enable register: enable each interrupt source 0x80050000 31 30 29 28 27 26 25 24 reserved tick gpiob[15] gpiob[14] gpioe gpiod 23 22 21 20 19 18 17 16 gpioc gpiob gpioa kbd 2wsi rtc wdt timer3 15 14 13 12 11 10 9 8 timer2 timer1 timer0 smc spi1 spi0 uart5 uart4 7 6 5 4 3 2 1 0 uart3 uart2 uart1 uart0 adc lcd usb pmu bits type function 0:29 r/w each bit of this register enables/disables corresponding interrupt sources. bit interrupt name description 28 tick rtc tick 27 gpiob[15] hotsync 26 gpiob[14] to the deep-sleep 25 gpioe gpioe 24 gpiod gpiod 23 gpioc gpioc 22 gpiob gpiob 21 gpioa gpioa 20 kbd keyboard controller 19 2wsi 2wsi 18 rtc real time clock controller 17 wdt watch dog timer 16 timer3 timer3 15 timer2 timer2 14 timer1 timer1 13 timer0 timer0 12 smc smc 11 spi1 spi1 10 spi0 spi0 9 uart5 uart5 8 uart4 uart4 7 uart3 uart3 6 uart2 uart2 5 uart1 uart1 4 uart0 uart0 3 adc adc 2 lcd lcd controller 1 usb usb controller 0 pmu power management unit 0 = disable interrupt (default) 1 = enable interrupt
amba peripherals (interrupt controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 110 - 9.2.1.2 direction register: interrupt source will trigger nirq or nfiq 0x80050004 31 30 29 28 27 26 25 24 reserved tick gpiob[15] gpiob[14] gpioe gpiod 23 22 21 20 19 18 17 16 gpioc gpiob gpioa kbd 2wsi rtc wdt timer3 15 14 13 12 11 10 9 8 timer2 timer1 timer0 smc spi1 spi0 uart5 uart4 7 6 5 4 3 2 1 0 uart3 uart2 uart1 uart0 adc lcd usb pmu bits type function 0:29 r/w each bit of this register indicates whether it is irq or fiq for corresponding interrupt sources. 0 = irq (default) 1 = fiq 9.2.1.3 status register: current interrupt request status (read-only) 0x80050008 31 30 29 28 27 26 25 24 reserved tick gpiob[15] gpiob[14] gpioe gpiod 23 22 21 20 19 18 17 16 gpioc gpiob gpioa kbd 2wsi rtc wdt timer3 15 14 13 12 11 10 9 8 timer2 timer1 timer0 smc spi1 spi0 uart5 uart4 7 6 5 4 3 2 1 0 uart3 uart2 uart1 uart0 adc lcd usb pmu bits type function 0:29 r each bit of this register indicates whether irq(or fiq) is generated or not. masked bit by enable register shows always ?0?. 0 = no interrupt request (default) 1 = interrupt pending 9.2.1.4 irqfiq register: current irq/fiq status (read-only) 0x80050020 7 6 5 4 3 2 1 0 reserved irq fiq bits type function 0:1 r bit 0 indicates current status of nfiq. bit 1 indicates current status of nirq. 0 = request pending 1 = no request (default)
amba peripherals (interrupt controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 111 - 9.2.2 interrupt control the interrupt controller provides interrupt request status, interrupt enable and interrupt direction selection registers. the enable register is used to determine whether or not an active interrupt source should generate an interrupt request to the processor. all bits are cleared by system reset. the interrupt request status indicates whether or not the interrupt source is causing a processor interrupt. the direction register is used to determine which interrupt request is generated to the cpu. if the bit is set, fiq request is activated. all bits are cleared by system reset. tic registers are used only for the production test. tic input select register is used to drive interrupt request sources by cpu. when this register is set, tic register bits are regarded as interrupt sources. this bit is cleared by system reset and should be cleared in normal operation.
amba peripherals (interrupt controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 112 -
amba peripherals (usb) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 113 - 9.3 usb slave interface this section describes the implementation-specific options of usb protocol for a device controller. it is assumed that the user has knowledge of the usb standard. this usb device controller (usbd) is chapter 9 (of usb specification) compliant, and supports standard device requests issued by the host. the user should refer to the universal serial bus specification revision 1.1 for a full understanding of the usb protocol and its operation. (the usb specification 1.1 can be accessed via the world wide web at: http://www.usb.org ). the usbd is a universal serial bus device controller (slave, not hub or host controller) which supports three endpoints and can operate half-duplex at a baud rate of 12 mbps. endpoint 0,by default is only used to communicate control transactions to configure the usbd after it is reset or physically connected to an active usb host or hub. endpoint 0's responsibilities include connection, address assignment, endpoint configuration and bus numeration. the connected host that can get a device descriptor stored in usbd?s internal rom via endpoint 0 configures the usbd. the usbd uses two separate 32 x 8 bit fifo to buffer receiving and transmitting data to/from the host. the cpu can access the usbd using interrupt controller, by setting the control register appropriately. this section also defines the interface of usbd and cpu. features ? full universal serial bus specification 1.1 compliant. ? receiver and transceiver have 32 bytes fifo individually (this supports maximum data packet size of bulk transfer). ? internal automatic fifo control logic. (according to fifo status, the usbd generates interrupt service request signals to the cpu) ? supports high-speed usb transfer (12mbps). ? there are two endpoints of transmitter and receiver respectively, totally three endpoints including endpoint 0 that has responsibility of the device configuration. ? cpu can access the internal usb configuration rom storing the device descriptor for hand-held pc (hpc) by setting the predefined control register bit. ? usb protocol and device enumeration is performed by internal state-machine in the usbd. ? the usbd only supports bulk transfer of 4-transfer type supported by usb for data transfer. ? endpoint fifo (tx, rx) has the control logic preventing fifo overrun and under run error. note product id: 7210 vendor id: 05b4 * can be modified
amba peripherals (usb) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 114 - 9.3.1 block diagram conf igurat ion rom (device descriptor) dev (device interface) endpoint 1 (receive fifo) endpoint 2 (transmit fifo) amba interface sie (serial interface engine) us b transceiv er dmac request signal fast apb i/f ausbp ausbn figure 9-9. usb block diagram the usb, figure 9-9. usb block diagram comprises the serial interface engine (sie) and device interface (dev). the sie connects to the usb through a bus transceiver, and performs nrzi conversion, bit un-stuffing, crc checking, packet decoding and serial to parallel conversion of the incoming data stream. in outgoing data, it does the reverse, that is, parallel to serial of outgoing data stream and packetizing the data, crc generation, bit stuffing and nrzi generation. the dev provides the interface between the sie and the device's endpoint fifo, rom storing the device descriptor. the dev handles the usb protocol, interpreting the incoming tokens and packets and collecting and sending the outgoing data packets and handshakes. the endpoints fifo (rx, tx) give the information of their status (full/ empty) to the amba interface and amba i/f enable the cpu to access the fifo's status register and the device descriptor stored in rom. the amba interface generates a fifo read/write strobe without fifo's errors, based on apb signal timing. in case of data transmitting through tx fifo (when usb generates an out token, amba i/f generates interrupt to cpu), the user should set the transmitting enable bit in the control register. if the error of fifo (rx: overrun, tx: under-run) occurs, the amba i/f cannot generate fifo read/ write.
amba peripherals (usb) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 115 - 9.3.2 external signals pin name type description usbp i/o usb transceiver signal for p+ usbn i/o usb transceiver signal for n+ refer to figure 2-1. 208 pin diagram. 9.3.3 registers address name width default description 0x8005.1000 gctrl 4 0x0 usb global configuration register 0x8005.1004 epctrl 21 0x0 endpoint control register 0x8005.1008 intmask 10 0x3ff interrupt mask register 0x8005.100c intstat 20 0x0 interrupt status register 0x8005.1018 devid 32 0x721005b4 device id register 0x8005.101c devclass 32 0xffffff device class register 0x8005.1020 intclass 32 0xffffff interface class register 0x8005.1024 setup0 32 - setup device request lower address 0x8005.1028 setup1 32 - setup device request upper address 0x8005.102c endp0rd 32 - endpoint0 read address 0x8005.1030 endp0wt 32 - endpoint0 write address 0x8005.1034 endp1rd 32 - endpoint1 read address 0x8005.1038 endp2wt 32 - endpoint2 write address table 9-4 usb slave interface register summary
amba peripherals (usb) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 116 - 9.3.3.1 gctrl 0x8005.1000 31 4 3 2 1 0 reserved transel wback resume dmadis bits type function 3 r/w forced suspend mode setting ?1? : forced suspend enable ?0? : foced suspend disable. and, normal operation or normal suspend enable. 2 r/w writeback mode for interrupt status register. ?1? : writeback erase enable. ?0? : writeback erase disable. 1 r/w this enables remote resume capab ilities. when this bi t set, usb drives remote resume signaling. should be cleared to stop resume 0 r dma disable bit. HMS30C7210 does not support dma, so value of this bit (logic 1) is not changeable 9.3.3.2 epctrl 0x8005.1004 31 21 20 19 18 17 16 15 14 13 12 reserved clr2 clr1 clr0 e2txb e2snd e2nk e2st e2en 11 10 9 8 7 4 3 2 1 0 e1rcv e1nk e1st e1en e0txb e0nk e0st e0tr e0en bits type function 21 r/w read ready signal control for endpoint 2 ?1? : read ready signal operation disabled. (always not-ready) ?0? : read ready signal operation enabled. 20 r/w clear endpoint2 fifo pointer(auto cleared by hardware). 19 r/w clear endpoint1 fifo pointer(auto cleared by hardware). 18 r/w clear endpoint0 fifo pointer(auto cleared by hardware). 17~1 6 r/w usb can transmit non maximum sized packet. this field contains the residue byte which should be transmitted. 15 r/w this bit enables non maximum sized packet transfer. after non maximum sized packet transfer, this bit is auto cleared and return to maximum packet size transfer mode. 14 r/w when this bit is set, and endpoint2 is not enabled, usb should send nak handshake 13 r/w when this bit is set, and endpoint2 is not enabled, usb should send stall handshake 12 r/w enable endpoint2 as in endpoint 11 r/w this bit must be zero. so only maximum packet size rx transfer mode is supported. this means rx (host out) data packet size is fixed to 32 bytes only. 10 r/w when this bit is set, and endpoint1 is not enabled, usb should send nak handshake 9 r/w when this bit is set, and endpoint1 is not enabled, usb should send stall handshake 8 r/w enable endpoint1 as out endpoint 7~4 r/w this bit stores the byte count which should be transmitted to host when in token is received (exception :: when this bit is 0, 8 byte are transferred) 3 r/w when this bit is set, and endpoint0 is not enabled, usb should send nak handshake 2 r/w when this bit is set, and endpoint0 is not enabled, usb should send stall handshake 1 r/w when this bit1, endpoint0 is configured to in endpoint. (others out endpoint) 0 r/w enable endpoint0
amba peripherals (usb) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 117 - 9.3.3.3 intmask 0x8005.1008 31 10 9 8 7 6 5 4 3 2 1 0 reserved e0stl sus reset e2em e1ov e1fu e0em e0ov e0fu set bits type function 9 r/w mask endpoint0 stall interrupt 8 r/w mask suspend interrupt 7 r/w mask usb cable reset interrupt 6 r/w mask endpoint2 empty interrupt 5 r/w mask endpoint1 overrun interrupt (may not be used) 4 r/w mask endpoint1 full interrupt 3 r/w mask endpoint0 empty interrupt 2 r/w mask endpoint0 overrun interrupt (may not be used) 1 r/w mask endpoint0 full interrupt 0 r/w mask endpoint0 setup token received interrupt 9.3.3.4 intstat 0x8005.100c 31 20 19 14 13 0 reserved ep1rxbyte ep0rxbyte 9 8 7 6 5 4 3 2 1 0 e0stl sus reset e2em e1ov e1fu e0em e0ov e0fu set bits type function 19~1 4 r/w currently remained byte in endpoint1 receive fifo which should be read by host 13~1 0 r/w currently remained byte in endpoint0 receive fifo which should be read by host 9 r/w endpoint0 stall interrupt 8 r/w suspend interrupt 7 r/w usb cable reset interrupt 6 r/w endpoint2 empty interrupt 5 r/w endpoint1 overrun interrupt (may not be used) 4 r/w endpoint1 full interrupt 3 r/w endpoint0 empty interrupt 2 r/w endpoint0 overrun interrupt (may not be used) 1 r/w endpoint0 full interrupt 0 r/w endpoint0 setup token received interrupt
amba peripherals (usb) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 118 - 9.3.3.5 devid 0x8005.1018 bits type function 31:0 r/w usb core can change device id field by writing appropriate device id value to this register 9.3.3.6 devclass 0x8005.101c bits type function 23:0 r/w usb core can change device class field by writing appropriate device id value to this register 9.3.3.7 intclass 0x8005.1020 bits type function 23:0 r/w usb core can change interface class field by writing appropriate device id value to this register while usb device configuration process, host requests descriptors. this usb block has a hard-wired descriptor rom, but there are 3 fields (whole 10 bytes size) user adjustable. [device descriptor] * see usb spec. 1.1 (9.6 standard usb descriptor definitions) for more detail offset (byte) initial value description adjustable h00 h12 length h01 h01 device h02 h00 spec version 1.00 h03 h01 spec version h04 hff device class yes h05 hff device sub-class yes h06 hff vendor specific protocol yes h07 h08 max packet size h08 hb4 vendor id yes h09 h05 vendor id (05b4) for hme yes h0a h02 product id yes h0b h72 product id (7210) for hme7210 yes h0c h01 device release # h0d h00 device release # h0e h00 manufacturer index string h0f h00 product index string h10 h00 serial number index string h11 h01 number of configurations * devid register has 32-bit width and it covers vendor id to product id (offset from h08 to h0b): devid [31:24] ? h0b, devid [2 3:16] ? h0a, devid [15:8] ? h09, devid [7:0] ? h08 * devclass register has 24-bit width and it covers device class to vendor specific protocol (offset from h04 to h06): devclass [23:16] ? h06, devclass [15:8] ? h05, devclass [7:0] ? h04
amba peripherals (usb) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 119 - [configuration descriptor] offset (byte) initial value description adjustable h00 h09 length of this descriptor h01 h02 configuration (2) h02 h20 total length includes endpoint descriptors h03 h00 total length high byte h04 h01 number of interfaces h05 h01 configuration value for this one h06 h00 configuration - string h07 h80 attributes - bus powered, no wakeup h08 h32 max power - 100 ma is 50 (32 hex) h09 h09 length of the interface descriptor h0a h04 interface (4) h0b h00 zero based index 0f this interface h0c h00 alternate setting value (?) h0d h02 number of endpoints (not counting 0) h0e hff interface class, ff is vendor specific yes h0f hff interface sub-class yes h10 hff interface protocol yes h11 h00 index to string descriptor for this interface h12 h07 length of this endpoint descriptor h13 h05 endpoint (5) h14 h01 endpoint direction (00 is out) and address h15 h02 transfer type ? h02 = bulk h16 h20 max packet size - low : 32 byte h17 h00 max packet size ? high h18 h00 polling interval in milliseconds (1 for iso) h19 h07 length of this endpoint descriptor h1a h05 endpoint (5) h1b h82 endpoint direction (80 is in) and address h1c h02 transfer type ? h02 = bulk h1d h20 max packet size - low : 32 byte h1e h00 max packet size ? high h1f h00 polling interval in milliseconds (1 for iso) * see usb spec. 1.1 (9.6 standard usb descriptor definitions) for more detail * the descriptor has 4 parts : configuration, interface, endpoint1, endpoint2 (doubled lines) [string descriptor] offset initial value description adjustable h0 h02 size in bytes h1 h03 string type (3) * this index zero string descriptor means a kind of look up table. as there is no other string descriptor and as there is no f urther information in this descriptor, usb block does not support strings. (all string index fields are filled with zero)
amba peripherals (usb) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 120 - 9.3.3.8 setup0 / setup1 0x8005.1024 / 0x8005.1028 bits type function 31:0 r/w usb core can accept vendor specific protocol command using endpoint0. this register contains previously received setup device request value (64-bit wide, half in each register) below is request format from host when configuration. [standard device request format] bmrequesttype brequest wvalue windex wlength byte 0 byte 1 byte 2 / byte 3 byte 4 / byte 5 byte 6 / byte 7 when host sends request to usb device, this usb block handles a few requests by sie (serial interface engine). this is the condition of requests which this usb sie can handle. ? request type must be standard (b00): see usb spec. 9.3 table 9-2 ?format of setup data? for more detail. offset 0 (bmrequesttype field) d[6:5] (type) ; 00 ? standard, 01 class, 10 ? vendor, 11 ? reserved. ? request must be one of these: get_descriptor, set_address, set_interface, set_configuration, get_interface, get_configuration and get_status. so for requests other than above, HMS30C7210 usb sets 9.2.5.4 intstat [0] and it means host sent setup request that usb sie cannot handle by itself and these 9.5.5.8 setup0 and setup1 resister hold device request data (8 bytes : 64 bit described above). this function is to handle standard requests that sie cannot handle and to handle vendor specific requests. * note: 9.2.5.4 intstat [0] bit will not go ?high? in case of setup request if sie can handle that request by itself.
amba peripherals (usb) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 121 - 9.3.3.9 endp0rd 0x8005.102c bits type function 31:0 r/w each endpoint 0 fifo read 9.3.3.10 endp0wt 0x8005.1030 bits type function 31:0 r/w each endpoint 0 fifo write 9.3.3.11 endp1rd 0x8005.1034 bits type function 31:0 r/w each endpoint 1 fifo read 9.3.3.12 endp2wt 0x8005.1038 bits type function 31:0 r/w each endpoint 2 fifo write
amba peripherals (usb) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 122 - 9.3.4 theory of operation the magnachip usb core enables a designer to connect virtually any device requiring incoming or outgoing pc data to the universal serial bus. as illustrated in figure 9-1: usb block diagram, the usb core comprises two parts, the sie and dev. the sie connects to the universal serial bus via a bus transceiver. the interface between the sie and the dev is a byte-oriented interface that exchanges various types of data packets between two blocks. serial interface engine the sie converts the bit-serial, nrzi encoded and bit-stuffed data stream of the usb into a byte and packet oriented data stream required by the dev. as shown in figure 9-2: usb serial interface engine, it comprises seven blocks: digital phase lock loop, input nrzi decode and bit-unstuff, packet decoder, packet encoder, output bit stuff and nrzi encode, counters, and the crc generation & checking block. each of the blocks is described in the following sections. nrzi decoder (input bit unstuff) nrzi encoder (output bit stuff) counter crc generation & checking packet decoder digital phase lock loop usb transceiver packet encoder device interface figure 9-10. usb serial interface engine digital phase lock loop the digital phase lock loop module takes the incoming data signals from the usb, synchronizes them to the 48mhz input clock, and then looks for usb data transitions. based on these transitions, the module creates a divide-by-4 clock called the usbclock. data is then output from this module synchronous to the usbclock. input nrzi decode and bit-unstuff the input nrzi decodes and bit-unstuff module extracts the nrzi encoded data from the incoming usb data. transitions on the input serial stream indicate a 0, while no transition indicates a 1. six ones in a row cause the transmitter to insert a 0 to force a transition, therefore any detected zero bit that occurs after six ones is thrown out.
amba peripherals (usb) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 123 - packet decoder the packet decoder module receives incoming data bits and decodes them to detect packet information. it checks that the pid (packet id) is valid and was sent without error. after decoding the pid, the remainder of the packet is split into the address, endpoint, and crc5 fields, if present. the crc checker is notified to verify the data using the incoming crc5 field. if the packet is a data packet, the data is collected into bytes and passed on with an associated valid bit. table 9-1: supported pid types shows the pid types that are decoded (marked as either receive or both). at the end of the packet, either the packetok or packetnotok signal is asserted. packetnotok is asserted if any error condition arose (bad valid bit, bit-stuff, bad pid, wrong length of a field, crc error, etc.). pid type value send/receive pid type value send/receive out 4'b0001 receive data1 4'b1011 both in 4'b1001 receive ack 4'b0010 both sof 4'b1101 receive nak 4'b1010 send setup 4'b0000 receive stall 4'b1110 send data0 4'b0011 both pre 4'b1100 receive table 9-5. usb supported pid types packet encoder the packet encoder creates outgoing packets based on signals from the dev. table 9-1: supported pid types shows the pid types that can be encoded (marked as send or both). for each packet type, if the associated signal sends type is received from the dev, the packet is created and sent. upon completion of the packet, packettypesent is asserted to inform the dev of the successful transmission. the packet encoder creates the outgoing pid, grabs the data from the dev a byte at a time, signals the crc generator to create the crc16 across the data field, and then sends the crc16 data. the serial bits are sent to the output bit stuff and nrzi encoder. output bit stuff and nrzi encoder the output bit stuff and nrzi encoder takes the outgoing serial stream from the packet encoder, inserts stuff bits (a zero is inserted after six consecutive ones), and then encodes the data using the nrzi encoding scheme (zeroes cause a transition, ones leave the output unchanged). counter block the counter block tracks the incoming data stream in order to detect the following conditions: reset, suspend, and turnaround. it also signals to the transmit logic (output nrzi and bit stuff) when the bus is idle so transmission can begin. generation and checking block the generation and checking block checks incoming crc5 and crc16 data fields, and generates crc16 across outgoing data fields. it uses the crc polynomial and remainder specified in the usb specification version 1.1.
amba peripherals (usb) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 124 - device interface the dev shown in figure 9-3: device interface works at the packet and byte level to connect a number of endpoints to the sie. it understands the usb protocol for incoming and outgoing packets, so it knows when to grab data and how to correctly respond to incoming packets. a large portion of the dev is devoted to the setup, configuration, and control features of the usb. as shown in figure 9-3: device interface the dev is divided into three blocks: device controller, device rom, and start of frame. the three blocks are described in the following sections. device controller ctl s ta rt o f fra m e g e n e ra tio n sof endpoints sie figure 9-1 usb device interface device controller device controller the device controller contains a state machine that understands the usb protocol. the (sie) provides the device controller with the type of packet, address value, endpoint value, and data stream for each incoming packet. the device controller then checks to see if the packet is targeted to the device by comparing the address/endpoint values with internal registers that were loaded with address and endpoint values during the usb enumeration process. assuming the address/endpoint is a match, the device controller then interprets the packet. data is passed on to the endpoint for all packets except setup packets, which are handled specially. data toggle bits (data0 and data1 as defined by the usb spec) are maintained by the device controller. for in data packets (device to host) the device controller sends either the maximum number of bytes in a packet or the number of bytes available from the endpoint. all packets are acknowledged as per the spec. for setup packets, the incoming data is extracted into the relevant internal fields, and then the appropriate action is carried out. table 9-2: supported setup requests lists the types of setup operations that are supported. setup request value supported setup request value supported get status 0 device, interface, endpoint get configuration 8 device clear feature 1 not supported set configuration 9 device set feature 3 not supported get interface 10 device set address 5 device set interface 11 device get descriptor 6 device synch frame 12 not supported set descriptor 7 not supported table 9-6 usb supported setup requests start of frame the start of frame logic generates a pulse whenever either the incoming start of frame (sof) packet arrives or approximately 1 ms after it the last one arrived. this allows an isochronous endpoint to stay in sync even if the sof packet has been
amba peripherals (usb) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 125 - garbled. 9.3.5 endpoint fifos (rx, tx) each endpoint fifo has the specific number of fifo depth according to data transfer rate. in case of maximum packet size for bulk transfer is 32 bytes that is supported in usbd. each fifo generates data ready signals (means fifo not full or fifo not empty) to amba if. it contains the control logic for transferring 4 bytes at a read/write strobe generated by amba to obtain better efficiency of amba bus.
amba peripherals (usb) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 126 -
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 127 - 9.4 adc interface controller HMS30C7210 has internal adc and adc interface logic for analog applications of touch panel interface and general purpose. if user doesn?t need these applications or want to use for other functions, there?s a direct adc control register available. all channels can be used for general purpose application. adc operating clock is ?aclk? called as ?pclk? in amba peripherals. adc sampling clock is ?oclk?. it is about 8khz. features ? 3-channel 10-bit adc. ? 8-sample data per one sampling point of touch panel (channel 0,1) ? 4-sample data per one sampling point of general purpose channel(channel 2) ? manual and auto adc power down mode ? adc input range : adcvss ~ adcvref ? conversion time : 4.33usec (@ 3.6923mhz)) apb i/f 8khz generator calibration time control longcal oclk trate control trate[1:0] a/d converter adin[0] adin[1] adin[2] ad[9:0] ach[2:0] aiostop xdata0[9:0] xdata7[9:0] ydata0[9:0] ydata7[9:0] ch2data0[9:0] ch2data3[9:0] adc data control adcdirdata[9:0] directc adc operation control (channel/mode) interrupt control sshot inttp intch2 adc direct control directc touch drive control touchxp touchxn touchyp touchyn figure 9-11. block diagram of adc, adc i/f
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 128 - 9.4.1 external signals pin name* type** description adin[0] ai adc input. touch panel x-axis signal input or general purpose input adin[1] ai adc input. touch panel y-axis signal input or general purpose input adin[2] ai adc input. ch2 value input. adcvdd p adc analog vdd adcvss p adc analog vss adcvref ai adc reference voltage. touchxp o touch screen switch x-positive drive touchxn o touch screen switch x-negative drive touchyp o touch screen switch y-positive drive touchyn o touch screen switch y-negative drive refer to figure 2-1. 208 pin diagram. 9.4.2 registers address name width default description 0x8005.3000 adccr 8 0x80 adc control register 0x8005.3004 adctpcr 8 0x0 touch panel control register 0x8005.3008 adcbacr 8 0x0 ch2 control register 0x8005.3010 adcisr 8 0x0 adc interrupt status register 0x8005.3020 adcdircr 8 0x0 adc direct control register 0x8005.3024 adcdirdata 10 0x0 adc direct data read register 0x8005.3030 adctpxdr0 32 0x0 touch panel x data register 0 0x8005.3034 adctpxdr1 32 0x0 touch panel x data register 1 0x8005.3038 adctpydr0 32 0x0 touch panel y data register 0 0x8005.303c adctpydr1 32 0x0 touch panel y data register 1 0x8005.3040 adctpxdr2 32 0x0 touch panel x data register 2 0x8005.3044 adctpxdr3 32 0x0 touch panel x data register 3 0x8005.3048 adctpydr2 32 0x0 touch panel y data register 2 0x8005.304c adctpydr3 32 0x0 touch panel y data register 3 0x8005.3050 adcmbdata0 32 0x0 ch2 data register0 0x8005.3054 adcmbdata1 32 0x0 ch2 data register1 table 9-7. adc controller register summary
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 129 - 9.4.2.1 adc control register (adccr) 0x8005.3000 7 6 5 4 3 2 1 0 adcpd directc wait[3:2] sop longcal bits type function 7 r/w adc power down bit user can set adcpd to save power consumption by adc. this bit blocks the clock to adc and adc i/f, so they consumes no power when this bit is set to ?1?. but after writing this bit to ?0?, adc need about 10ms calibration time to normal operation. 0: normal mode 1: power down mode 6 r/w adc direct access control directc bit can be used for direct access from cpu to adc without interface function logic. all direct control signals are describe in adcdircr register field. if this bit is set to ?1?, cpu directly access adc through adcdircr and directly read adc result value through adcdirdata register. in this mode, adccr register except adcpd don?t affect to adc and adc i/f 0: no direct access mode 1: direct access mode 5:4 - reserved 3:2 r/w adc conversion wait time basically adc core converts analog data to digital data continuously in every 16 adc operation-clocks called as ?aclk?. wait bit field select data loading time of adc i/f logic because in certain case adc i/f logic can read wrong or unstable value from adc. ?no wait? informs that adc data loading clock period is equal to adc conversion clock period. ?2, 4 clock wait? informs that adc data loading clock period is longer than adc conversion clock period. wait[1:0] wait time a period of loading data clock 00 no wait equal to a period of adc conversion clock 01 2 clock wait more 2cycles of aclk 10 4 clock wait more 4cycles of aclk 11 reserved reserved *adc conversion clock is 16 cycles of aclk 1 r/w self operating power down bit it means that power down mode of adc ?not adc i/f- is controlled by tpen and ch2en in addition to adcpd. sop bit can be used for one-shot operation to save power. when this bit is set to ?1? and all adc functions aren?t enabled, so adc goes to power down mode. 0: no sop mode 1: sop mode 0 r/w long calibration time. longcal selects self-calibration time. initially this bit is set to ?0? .it means short calibration time (about 12 ms). but if first a couple of data were wrong value, user should select long calibration time (about 48 ms) by writing this bit set to ?1?. the default adc calibration time is 12 ms. but when it is needed, adc can be calibrated during 48ms with this bit. - calibration time t scal = 96 / f oclk = 12msec or t lcal = 384 / f oclk = 48msec 0: short calibration time (96 cycles of oclk*) 1: long calibration time (384 cycles of oclk)
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 130 - 9.4.2.2 adc touch panel control register (adctpcr) 0x8005.3004 7 6 5 4 3 2 1 0 tpen tintmsk swinvt sshot trate[1:0] bits type function 7 r/w touch panel read enable bit. if this bit is set to ?1?, touch panel function is enabled. 0: touch panel read disable 1: touch panel read enable 6 r/w touch panel read interrupt mask bit. writing this bit to ?1? enables generating of interrupt signal from touch panel data receiver. refer to adcisr[2] 0: interrupt disable 1: interrupt enable 5 - reserved 4 r/w touch panel drive signal inversion bit for flexibility. touchxm and touchym output initial value is ?0?. while touch panel x mode in progress, touchxm value is ?1?. also while touch panel y mode in progress, touchym value is ?1?. always touchxp and touchyp output value opposite to touchxm and touchym respectively. writing this bit to ?1? inverts the above. for example, touchxm output initial value change to ?1?. also while touch panel x mode in progress, touchxm value is ?0?. 0: no inversion 1: inversion 3 - reserved 2 r/w single touch panel read operation. normally, touch panel data read twice per 4-sample. but this bit is set to ?1?, touch panel data read just once per 4-sample and saving power to read touch panel. 0: data read twice. touch panel data is loaded into 1st and 2nd touch panel data registers. 1: data read once. touch panel data is loaded into just 1st touch panel data registers. 1:0 r/w touch panel data sampling rate. it depends on oclk of adc interface. trate[1:0] samples / sec description 00 50 samples / sec one sample per 160 cycles of oclk 01 100 samples / sec one sample per 80 cycles of oclk 10 200 samples / sec one sample per 40 cycles of oclk 11 400 samples / sec one sample per 20 cycles of oclk
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 131 - 9.4.2.3 adc ch2 control register (adcch2cr) this register controls ch2 channel check operation. 0x8005.3008 7 6 5 4 3 2 1 0 ch2intmsk ch2en bits type function 7:2 - reserved should be set to ?0? 1 r/w ch2 channel interrupt mask bit writing this bit to ?1? enables generating interrupt signal from ch2 channel data register. refer to adcisr[1]. 0: interrupt disable 1: interrupt enable 0 r/w ch2 enable if this bit is set to ?1?, ch2 function is enabled. 0: ch2 channel disable 1: ch2 channel enable 9.4.2.4 adc interrupt status register (adcisr) 0x8005.3010 7 6 5 4 3 2 1 0 tp_int ch2_int bits type function 7:3 - reserved 2 r touch panel data interrupt flag. interrupt signal is generated at the end of ch2_mode after 4-sampling. read only valid and writing this bit to ?1? clear this flag. 0: interrupt was not generated or was cleared. 1: interrupt was generated. 1 r ch2 channel interrupt flag. interrupt signal is generated at the end of tpy_mode after 4-samling or 8-samlping. if sshot is set to ?0?, tp_int is generated at the end of 2 nd tpy_mode after 8-sampling of tpx and tpy respectively. but if sshot is set to ?1?, tp_int is generated at the end of 1 st tpy_mode after 4-sampling of tpx and tpy respectively. read only valid and writing this bit to ?1? clear this flag. 0: interrupt was not generated or was cleared 1: interrupt was generated. 0 - reserved
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 132 - 9.4.2.5 adc direct control register (adcdircr) 0x8005.3020 7 6 5 4 3 2 1 0 dir_aiostop dir_ach[2:0] bits type function 7 r/w direct aiostop when directc(adccr[6]) bit is set to ?1?, adc power down mode is controlled by dir_aiostop, not adcpd(adccr[7]). but if directc bit is ?0?, dir_aiostop doesn?t affected to adc power down mode. 0: normal mode in the direct access mode 1: power down mode in the direct access mode 6:3 - reserved should be set to ?0? 2:0 r/w direct adc channel when directc(adccr[6]) bit is set to ?1?, adc channel is controlled by dir_ach. dir_ach[2:0] channel description 001 channel 0 touch panel x 010 channel 1 touch panel y 100 channel 2 general purpose 9.4.2.6 adc direct data read register (adcdirdata) register can be used to read data from adc. 0x8005.3024 9 8 7 6 5 4 3 2 1 0 dir_ad[9:0] bits type function 9:0 r 10-bit ad conversion data
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 133 - 9.4.2.7 adc 1st touch panel data register 0x8005.3030 ? 0x8005.303c 25 24 23 22 21 20 19 18 17 16 xdata1: adctpxdr0[25:16], xdata3: adctpxdr1[25:16] ydata1: adctpydr0[25:16], ydata3: adctpydr1[25:16] 9 8 7 6 5 4 3 2 1 0 xdata0: adctpxdr0[9:0], xdata2: adctpxdr1[9:0] ydata0: adctpydr0[9:0], ydata2: adctpydr1[9:0] adctpxdr0: 0x8005.3030 bits type function 31:26 - reserved 25:16 r touch panel x data 10-bit, 2/4 of the first sample cycle (xdata1) 15:10 - reserved 9:0 r touch panel x data 10-bit, 1/4 of the first sample cycle (xdata0) adctpxdr1: 0x8005.3034 bits type function 31:26 - reserved 25:16 r touch panel x data 10-bit, 4/4 of the first sample cycle (xdata3) 15:10 - reserved 9:0 r touch panel x data 10-bit, 3/4 of the first sample cycle (xdata2) adctpydr0: 0x8005.3038 bits type function 31:26 - reserved 25:16 r touch panel y data 10-bit, 2/4 of the first sample cycle (ydata1) 15:10 - reserved 9:0 r touch panel y data 10-bit, 1/4 of the first sample cycle (ydata0) adctpydr1: 0x8005.303c bits type function 31:26 - reserved 25:16 r touch panel y data 10-bit, 4/4 of the first sample cycle (ydata3) 15:10 - reserved 9:0 r touch panel y data 10-bit, 3/4 of the first sample cycle (ydata2)
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 134 - 9.4.2.8 adc 2nd touch panel data register 0x8005.3040 ? 0x8005.304c 25 24 23 22 21 20 19 18 17 16 xdata5: adctpxdr2[25:16], xdata7: adctpxdr3[25:16] ydata5: adctpydr2[25:16], ydata7: adctpydr3[25:16] 9 8 7 6 5 4 3 2 1 0 xdata5: adctpxdr2[9:0], xdata6: adctpxdr3[9:0] ydata5: adctpydr2[9:0], ydata6: adctpydr3[9:0] adctpxdr2: 0x8005.3040 bits type function 31:26 - reserved 25:16 r touch panel x data 10-bit, 2/4 of the second sample cycle (xdata5) 15:10 - reserved 9:0 r touch panel x data 10-bit, 1/4 of the second sample cycle (xdata4) adctpxdr3: 0x8005.3044 bits type function 31:26 - reserved 25:16 r touch panel x data 10-bit, 4/4 of the second sample cycle (xdata7) 15:10 - reserved 9:0 r touch panel x data 10-bit, 3/4 of the second sample cycle (xdata6) adctpydr2: 0x8005.3038 bits type function 31:26 - reserved 25:16 r touch panel y data 10-bit, 2/4 of the second sample cycle (ydata5) 15:10 - reserved 9:0 r touch panel y data 10-bit, 1/4 of the second sample cycle (ydata4) adctpydr3: 0x8005.303c bits type function 31:26 - reserved 25:16 r touch panel y data 10-bit, 4/4 of the second sample cycle (ydata7) 15:10 - reserved 9:0 r touch panel y data 10-bit, 3/4 of the second sample cycle (ydata6)
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 135 - 9.4.2.9 adc ch2 data register (adcch2data) 0x8005.3050 ? 0x8005.3054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ch2data1: adcch2data0, ch2data3: adcch2data1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ch2data0: adcch2data0, ch2data2: adcch2data1 adcmbdata0: 0x8005.3050 bits type function 31:26 - reserved 25:16 r ch2 channel data 10-bit, 2/4 of the ch2 sample cycle (ch2data1) 15:10 - reserved 9:0 r ch2 channel data 10-bit, 1/4 of the ch2 sample cycle (ch2data0) adcmbdata1: 0x8005.3054 bits type function 31:26 - reserved 25:16 r ch2 channel data 10-bit, 4/4 of the ch2 sample cycle (ch2data3) 15:10 - reserved 9:0 r ch2 channel data 10-bit, 3/4 of the ch2 sample cycle (ch2data2)
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 136 - 9.4.3 operation 9.4.3.1 clock & power down mode the clock source of adc is the peripheral clock pclk. this is called the aclk and is controlled by the adcpd bit in adccr register. writing ?0? to the adcpd bit is that the pclk is connected to aclk. on the contrary, writing ?1? to this bit means that adc mode is power down mode. in this mode, the aclk is always ?0?. the data sampling clock of adc interface controller is the oclk. this clock has a frequency of f pclk / 461. a/d converter adcpd pclk aclk oclk generator oclk data sampling logic figure 9-12. adc clock & data sampling clock 9.4.3.2 operating stop condition & power down mode the adc can go to power down mode by blocking aclk and controlling aiostop. the aiostop is an enable signal of the adc. when this signal is low, the adc starts normal operation. by writing to ?0? to the adcpd bit, aiostop is set to ?0?. but if the sop bit in adccr register, the tpen in adctpcr register or ch2en in adcch2cr register should be set to ?1? in addition to the adcpd low. tpen or ch2en sop adcpd aiostop figure 9-13. adc operating stop condition
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 137 - 9.4.3.3 calibration time the adc needs calibration time for adc conversion start. the calibration time for the adc is about 10msec. when the longcal in adccr register is low, the calibration time is about 12msec. if the first a couple of data were wrong value, the adc is not stable yet. in this case, user should set ?1? to the longcal bit. long calibration time is about 48msec. 9.4.3.4 data sampling & loading time the data sampling frequency of the adcif is oclk. adc data is loaded into adctpxdr, adctpydr, adcch2dr registers four times per one period of oclk. when oclk is high, data loading is started after 90 cycles of aclk. the conversion clock of the adc is f aclk /16. user can select data loading cycle. the wait bits in adccr register determine a period of loading data. when the wait bits are ?0?, a period of loading data is equal to a period of adc conversion clock. when the wait bits are ?1? or ?2?, a period of it is more 2 or 4 cycles of aclk. 16/18/20 cycles of aclk oclk aclk_cnt[7:0] load_clk ad[9:0] adctpxdr0[31:0] adctpxdr1[31:0] 89 90 0 1 230 231 230 0 0x3ff 0x0000.03ff 0x03ff.03ff 0x0000.03ff 0x03ff.03ff figure 9-14. data loading timing
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 138 - 9.4.3.5 data sampling sequence one sampling cycle is consisted of oclk 20 cycles. mode, channel operation normally mode & channel of ch2 are generated once per sampling cycle. mode & channel of touch panel are generated twice per sampling cycle. but in this case, touch panel is dependent on sshot or trate. sshot operation normally touch panel data register is loaded twice. so touch panel data is loaded into 1 st and 2 nd touch panel data registers. if the sshot bit in adctpcr register is set high, touch panel data register is loaded just once for a point and saving power to read touch panel. so touch panel data is loaded into just 1 st touch panel data register. trate [1:0] operation these bits are in adctpcr register. if the trate bits are 2?b11, touch panel data registers are updated every sampling cycle. if the trate bits are 2?b10, touch panel data registers are updated once per 2 sampling cycles. if the trate bits are 2?b01, touch panel data registers are updated once per 4 sampling cycles. if the trate bits are 2?b10, touch panel data registers are updated once per 8 sampling cycles. oclk ach[2:0] ch2_mode tpx_mode tpy_mode touch_xp touch_xn touch_yp touch_yn 1st sampling cycle (20 cycles of oclk) 2nd sampling cycle 4 1 2 1 2 0 0 0 0 0 0 4 1 2 1 0 0 0 0 figure 9-15. data sampling sequence ? trate is 2?b11 / sshot is 1?b0 / swinvt is 1?b0
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 139 - oclk ach[2:0] ch2_mode tpx_mode tpy_mode touch_xp touch_xn touch_yp touch_yn 1st sampling cycle (20 cycles of oclk) 2nd sampling cycle 4 1 2 0 0 0 0 4 1 2 0 0 0 figure 9-16. data sampling sequence ? trate is 2?b11 / sshot is 1?b1 / swinvt is 1?b0 oclk ach[2:0] ch2_mode tpx_mode tpy_mode touch_xp touch_xn touch_yp touch_yn 1st sampling cycle (20 cycles of oclk) 2nd sampling cycle 4 1 2 1 2 0 0 0 0 0 0 4 1 0 0 figure 9-17. data sampling sequence ? trate is 2?b10 / sshot is 1?b0 / swinvt is 1?b1
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 140 - 9.4.3.6 interrupt control interrupt signal is generated at the end of ch2_mode, tpy_mode. for generating interrupt signal, the tintmsk bit in adctpcr register and the ch2intmsk bit in adcch2cr register are set high. if the sshot bit in adctpcr register is low, tp_int is generated at the end of 2 nd tpy_mode. as soon as adc 2 nd touch panel data registers is updated, tp_int is generated. but if the sshot bit in adctpcr register is high, tp_int is generated at the end of 1 st tpy_mode. as soon as adc 1 st touch panel data registers is updated, tp_int is generated. in case of ch2_mode, ch2_int is always generated at the end mb_mode. oclk ach[2:0] ch2_mode tpx_mode tpy_mode ch2_int tp_int 1st sampling cycle (20 cycles of oclk) 2nd sampling cycle 4 1 2 1 2 0 0 0 0 0 0 4 1 2 1 0 0 0 0 figure 9-18. interrupt generating timing ? trate is 2?b11 / sshot is 1?b0 oclk ach[2:0] ch2_mode tpx_mode tpy_mode ch2_int tp_int 2nd sampling cycle 4 1 2 0 0 0 0 4 1 0 0 0 2 1st sampling cycle (20 cycles of oclk) figure 9-19. interrupt generating timing ? trate is 2?b11 / sshot is 1?b1
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 141 - 9.4.3.7 direct access mode the cpu can directly access the adc. when the directc bit in adccr register is high, the direct control logic is enabled and the adc is directly connected by using adcdircr register. adc conversion data is loaded into adcdirdata register. the adcpd bit in adccr register should be set low to start this mode. directc direct control logic a/d converter ach[2:0] aiostop ad[9:0] enable figure 9-20. adc direct access mode 9.4.3.8 operation setup flow touch panel mode ? select swintv, sshot, trate[1:0] in adctpcr register. ? set tpen, tintmsk in adctpcr register. ? select wait[3:2], sop, longcal in adccr register. ? set adcpd to low in adccr register for starting. ? check tp_int in adcisr register. ch2 mode ? set ch2en, ch2intmsk in adcch2cr register. ? select wait[3:2], sop, longcal in adccr register. ? set adcpd to low in adccr register for starting. ? check ch2_int in adcisr register. direct access mode ? set directc in adccr register. ? select dir_ach[2:0] in adcdircr register. ? set dir_aiostop to low in adcdircr register. ? set adcpd to low in adccr register for starting. ? check dir_ad[9:0] in adcdirdata register 9.4.3.9 about touch panel board setup adctpcr register control functions related with touch panel interface. HMS30C7210 supports only external drive for touch panel (touchxp/touchxn/touchyp/touchyn), so prudent setting of this register is needed. for more information about touch panel setup, refer to ?HMS30C7210 h/w reference development kit reference board ver0.1? in www.magnachip.com web site.
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 142 - 9.4.4 a/d converter h35ad33s is a cmos(0.35 ? , 1-poly, 3-metal) 10-bit successive approximation a/d converter which has high speed, low power consumption. the adc has multiplexed 8 input channels. the serial output is configured to interface with standard shift registers. the differential analog voltage input allows for common-mode rejection or offset of the analog zero input voltage value. the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 10 bits of resolution features ? power supply: 3.3v ? resolution: 10 bits ? signal-to-noise ratio (snr): 54db ? 3 channels ? conversion speed: 230khz (@ 3.6923mhz) ? main clock: 3.6923 mhz ? power-down mode ? analog input range: avss~ avref ? cell size: 1000 ? x 1000 ? dvss dvdd avref avss avdd an2 [lsb] data[0] data[1] data[2] data[3] data[4] data[5] data[6] data[7] data[8] data[9] [msb] aclk auto-zero comparator 3 1bit per clock 11bit successive approximation register da1 da2 da3/4 4 bits 5 bits 2 bits 2 1 1 format converter 11 bits 10 bits 1 bits a/d conversion section clock & phase generator adc multi- plexer vin ach[1] ach[2] 3 analog input (an=0~3.3v) c1 c4 c2 c5 c3 c6 .c1~c3:10uf .c4~c6:2200pf .dvss=0v .dvdd=3.3v .avref=3.3v . r1,r2 < 1kohm ceramic capacitor charge capacitor .c1~c3:10uf .c4~c6:2200pf .dvss=0v .dvdd=3.3v .avref=3.3v . r1,r2 < 1kohm ceramic capacitor charge capacitor ceramic capacitor charge capacitor 10 bits an1 an0 ach[0] aiostop figure 9-21. block diagram of a/d converter
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 143 - 9.4.4.1 functional description this sar-type adc contains a sar register, an auto-zero comparator, three internal dac, mux(3x1), a format converter, a clock & phase generator, and a reference ladder & calibrator. the conversion rate ranges up to 1mhz. these blocks contained in adc can be described as follows: sar register this block is a successive approximation register which latches the output of comparator and generates the input of the internal dac. auto-zero comparator this comparator is able to reduce the offset error periodically and senses the difference between analog input and dac output. internal dac these dac generate analog reference voltage according to sar register output. multiplexer one of the eight channel can be selected by the control pins (ach[0] ~ ach[2]) format converter this format converter is to latch the 11-bit sar output data stream and convert it to a standard 10-bit binary format. clock & phase generator the outputs generated in clock & phase generator control sar-type adc conversion operation. reference ladder & calibration this reference ladder generates the analog reference voltage used by the internal dac. the reference ladder taps are adjusted by using an auto-calibration technique.
amba peripherals (adc interface controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 144 - 9.4.4.2 timing diagram adc starts data conversion after calibration time. analog input ( an0~an7 ) output data (data[9:0] ) analog input ( an0~an7 ) output data (data[9:0] ) sn- 1 sn avref t pwh t pwl 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 s n+ 1 unknown data datan data n- 2 t cal (aclk) (aiostop) main clock power up t c figure 9-22. timing diagram of a/d converter 9.4.4.3 electrical characteristics refer to ?chapter 11.3 a/d conver ter electrical characteristics?
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 145 - 9.5 uart/sir uart (universal asynchronous receiver/transmitter) of HMS30C7210 is functionally identical to the 16c550. on power-up, uart is set to character mode(non-fifo mode) and has a single tx/rx buffer. this uart can be put into an alternate mode (fifo mode) to relieve the cpu of excessive software overhead. in the fifo mode internal fifos are activated - receive fifo (16 bytes plus 3 bit of error data per byte) stores the received data and the error information of individual received data and transmit fifo(16 bytes) stores the data to be trainsmitted. all the logic is on the chip to minimize the system overhead and to maximize efficiency. the uart performs serial-to-parallel conversion on data characters received from a peripheral device or a modem, and parallel-to-serial conversion on data characters received from the cpu. the cpu can read the complete status of the uart at any time during the functional operation. status information reported includes the type and condition of the transfer operations being performed by the uart, as well as any error conditions (parity, overrun, framing, or break interrupt). the uart includes a programmable baud rate generator capable of dividing the timing reference clock input by divisors of 1 to 2 16 -1, and producing a 16x clock for driving the internal transmitter logic. provisions are also included to use this 16x clock to drive the receiver logic. the uart has complete modem-control capability, and a processor-interrupt system. interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link. features ? capable of running all existing 16c550 software (except uart0, uart1). ? after reset, all registers are identical to the 16c550 register set. (except uart0, uart1). ? the fifo mode transmitter and receiver are each buffered with 16 byte fifos to reduce the number of interrupts presented to the cpu. ? add or delete standard asynchronous communication bits (start, stop and parity) to or from the serial data. ? holding and shift registers in the 16c450 mode eliminate the need for precise synchronization between the cpu and serial data. ? independently controlled transmit, receive, line status and data set interrupts. ? programmable baud generator divides any input clock by 1 to 65535 and generates 16x clock ? independent receiver clock input. ? modem control functions (cts, rts, dsr, dtr, ri and dcd) (uart5 only). ? fully programmable serial-interface characteristics: ? 5-, 6-, 7- or 8-bit characters ? even, odd or no-parity bit generation and detection ? 1-, 1.5- or 2-stop bit generation and detection ? baud generation (dc to 230k baud) ? false start bit detection. ? complete status-reporting capabilities. ? line breaks generation and detection. ? internal diagnostic capabilities: ? loopback controls for communications link fault isolation ? full prioritized interrupt system controls.
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 146 - 9.5.1 external signals these uart pin names are same as HMS30C7210 top pin names. to get the information about pin number of uart signal at chip, refer to ?table 2-3 detail pin description?. pin name type description scrst [0] i uart 0 serial data inputs. serial data input from the communications link (peripheral device, modem or data set). scio [0] o uart 0 serial data outputs. composite serial data output to the communications link (peripheral, modem or data set). the usout signal is set to the marking (logic 1) state upon a master reset operation. scrst [1] i uart 1 serial data inputs scio [1] o uart 1 serial data outputs uart2rx i uart 2 serial data inputs uart2tx o uart 2 serial data outputs uart3rx i uart 3 serial data inputs uart3tx o uart 3 serial data outputs irda4rx i uart 4 serial data inputs irda4tx o uart 4 serial data outputs uart5rx i uart 5 serial data inputs uart5tx o uart 5 serial data outputs nuring i uart 5 ring input signal (wake-up signal to pmu). when low, this indicates that the modem or data set has received a telephone ring signal. the nuring signal is a modem status input whose condition can be tested by the cpu reading bit 6 (ri) of the modem status register. bit 6 is the complement of the nuring signal. bit 2 (teri) of the modem status register indicates whether the nuring input signal has changed from a low to a high state since the previous reading of the modem status register. nudtr o uart 5 data terminal ready. when low, this informs the modem or data set that the uart is ready to establish communication link. the nudtr output signal can be set to an active low by programming bit 0 (dtr) of the modem control register to high level. nucts i uart 5 clear to send input. when low, this indicates that the modem or data set is ready to exchange data. the nucts signal is a modem status input whose conditions can be tested by the cpu reading bit 4 (cts) of the modem status register. bit 4 is the complement of the nuring signal. bit0 (dcts) indicates whether the nucts input has changed state since the previous reading of the modem status register. nucts has no effect on the transmitter. nurts o uart 5 request to send. when low, this informs the modem or data set that the uart is ready to exchange data. the nurts output signal can be set to an active low by programming bit 1 (rts) of the modem control register. nudsr i uart 5 data set ready input. when low, this indicates that the modem or data set is ready to establish the communications link with the uart. the nudsr signal is a modem status input whose conditions can be tested by the cpu reading bit 5 (dsr) of the modem status register. bit 5 is the complement of the nudsr signal. bit 1(ddsr) of modem status register indicates whether the nudsr input has changed state since the previous reading of the modem status register. nudcd i uart 5 data carrier detect input. when low, indicates that the data carrier has been detected by the modem data set. the signal is a modem status input whose condition can be tested by the cpu reading bit 7 (dcd) of the modem status register. bit 7 is the complement of the signal. bit 3 (ddcd) of the modem status register indicates whether the input has changed state since the previous reading of the modem status register. nudcd has no effect on the receiver. refer to figure 2-1. 208 pin diagram.
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 147 - 9.5.2 registers address name width default description 0x8005.4000 u0base - - uart 0 base 0x8005.5000 u1base - - uart 1 base 0x8005.6000 u2base - - uart 2 base 0x8005.7000 u3base - - uart 3 base 0x8005.8000 u4base - - uart 4 base 0x8005.9000 u5base - - uart 5 base rbr 8 0x00 receiver buffer register (dlab = 0, read only) thr 8 0x00 transmitter holding register (dlab = 0, write only) uxbase+0x00 dll 8 0x00 divisor latch least significant byte (dlab = 1, read/write) ier 8 0x00 interrupt enable register (dlab = 0, read/write) uxbase+0x04 dlm 8 0x00 divisor latch most significant byte (dlab = 1, read/write) iir 8 0x01 interrupt identification register (read only) uxbase+0x08 fcr 8 0x00 fifo control register (write only) uxbase+0x0c lcr 8 0x00 line control register (read/write) uxbase+0x10 mcr 3 0x00 modem control register (read/write) uxbase+0x14 lsr 8 0x60 line status register (read/write) uxbase+0x18 msr 8 0x00 modem status register (read/write) uxbase+0x1c scr 8 0x00 scratch register (read/write) uxbase+0x30 ucr 6 0x00 uart configuration register (read/write) table 9-8 uart/sir register summary
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 148 - 9.5.2.1 rbr rbr is the receive buffer register and stores the data from serial input. this register is read-only and can be accessed when dlab(bit7 of line control register) is set to 0. uxbase+0x00 7 6 5 4 3 2 1 0 receive data bit 7 ~ receive data bit 0 bits type function 7:0 r receive byte that is received from serial input. 9.5.2.2 thr thr is the transmit buffer register and stores the data to be transmitted through serial output. this register is write-only and can be accessed when dlab(bit7 of line control register) is set to 0. uxbase+0x00 7 6 5 4 3 2 1 0 transmit data bit 7 ~ transmit data bit 0 bits type function 7:0 w transmit byte that is transmitted through serial output. 9.5.2.3 dll dll is the divisor latch least significant byte register and used to set the lower 8- bit of 16-bit baud-rate divisor value. uxbase+0x00 7 6 5 4 3 2 1 0 baud-rate divisor bit 7 ~ baud-rate divisor bit 0 bits type function 7:0 r/w lower 8-bit of 16-bit baud-rate divisor.
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 149 - 9.5.2.4 ier ier is the interrupt enable reigster and enables the five types of uart interrupts. each interrupt can individually activate the interrupt (intuart) output signal. it is possible to totally disable the interrupt enable register (ier). similarly, setting bits of the ier register to logic 1 enables the selected interrupt(s). disabling an interrupt prevents it from being indicated as active in the iir and from activating the intuart output signal. all other system functions operate in their normal manner, including the setting of the line status and modem status registers. table 13-6: summary of registers on page 13-10 shows the contents of the ier. details on each bit follow. uxbase+0x04 7 6 5 4 3 2 1 0 0 0 0 0 ms intr ls intr tx empty intr data rdy intr bits type function 7 r/w 0 6 r/w 0 5 r/w 0 4 r/w 0 3 r/w enables the modem status interrupt when set to logic 1. 2 r/w enables the receiver line status interrupt when set to logic 1. 1 r/w enables the transmitter holding register empty interrupt when set to logic 1. 0 r/w enables the received data available interrupt (and time-out interrupts in the fifo mode) when set to logic 1. 9.5.2.5 dlm dlm is the divisor latch most significant byte register and used to set the upper 8- bit of 16-bit baud-rate divisor value. uxbase+0x00 7 6 5 4 3 2 1 0 baud-rate divisor bit 15 ~ baud-rate divisor bit 8 bits type function 7:0 r/w upper 8-bit of 16-bit baud-rate divisor.
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 150 - 9.5.2.6 iir in order to provide minimum software overhead during data character transfers, the uart prioritizes interrupts into four levels and records these in the interrupt identification register. the four levels of interrupt conditions are, in order of priority ? receiver line status ? received data ready ? transmitter holding register empty ? modem status bit3~bit0 of the iir are used to identify the highest priority interrupt that is pending. bit0 represents whether the interrupt is pending or not ? if bit0 is 1, no interrupt occurs now and if bit0 is 0, an interrupt is pending and the iir contents may be used as a pointer to the appropriate interrupt service routine. if two interrupts occurs simultaneously, bit3~bit0 of iir represents the higher priority number between these two interrupts. these bits represent the lower priority interrupt after cpu clears the higher priority interrupt. when the cpu accesses the iir, the uart freezes all interrupts and indicates the highest priority pending interrupt to the cpu. while this cpu access is occurring, the uart records new interrupts, but does not change its current indication until the access is complete. bit7~bit6 of iir are set to 1, when bit0 of fcr(fifo control register) is 1, otherwise these two bits are set to 0. uxbase+0x08 7 6 5 4 3 2 1 0 fifo en 0 0 intr id intr pend function bits type value prioriy level interrupt type interrupt source interrupt reset condition 0001 - none none - 0110 highest receiver line status overrun error or parity error or framing error or break interrupt reading the line status register reading the line status register 0100 second received data available receiver data available or trigger level reached reading the receiver buffer register or the fifo drops below the trigger level 1100 second character time- out indication no characters have been removed from or input to the rcvr fifo during the last 4 character times and there is at least 1 character in it during this time reading the receiver buffer register 0010 third transmitter holding register empty transmitter holding register empty reading the iir register (if source of interrupt) or writing into the transmitter holding register 3:0 r 0000 fourth modem status clear to send or data set ready or ring indicator or data carrier detect reading the modem status register
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 151 - 9.5.2.7 fcr this is a write-only register at the same location as the iir (the iir is a read-only register). this register is used to enable the fifos, clear the fifos and set the rcvr fifo trigger level. uxbase+0x08 7 6 5 4 3 2 1 0 rcvr trig level - - - xmit reset rcvr reset fifo en bits type function 7:6 w these two bits sets the trigger level for the rcvr fifo interrupt value rcvr fifo trigger level (bytes) 00 01 01 04 10 08 11 14 5:3 - reserved 2 w writing 1 resets the transmitter fifo counter logic to 0. the shift register is not cleared. the 1 that is written to this bit position is self-clearing 1 w writing 1 resets the receiver fifo counter logic to 0. the shift register is not cleared. the 1 that is written to this bit position is self-clearing 0 w writing 1 enables both the xmit and rcvr fifos. resetting fcr0 will clear all bytes in both fifos. when changing from fifo mode to 16c450 mode and vice versa, data is automatically cleared from the fifos. this bit must be a 1 when other fcr bits are written to or they will not be programmed
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 152 - 9.5.2.8 lcr the system programmer specifies the format of the asynchronous data communications exchange and set the divisor latch access bit via the line control register (lcr). the programmer can also read the contents of the line control register. the read capability simplifies system programming and eliminates the need for separate storage in system memory of the line characteristics. uxbase+0x0c 7 6 5 4 3 2 1 0 dlab set break stick parity even parity parity enable stopbit number word length select bits type function 7 this bit is the divisor latch access bit (dlab). it must be set high (logic 1) to access the divisor latches of the baud generator during a read or write operation. it must be set low (logic 0) to access the receiver buffer, the transmitter holding register or the interrupt enable register 6 this bit is the break control bit. it causes a break condition to be transmitted to the receiving uart. when it is set to logic 1, the serial output (sout) is forced to the spacing (logic 0) state. the break is disabled by setting logic 0. the break control bit acts only on sout and has no effect on the transmitter logic. note: this feature enables the cpu to alert a terminal in a computer communications system. if the following sequence is followed, no erroneous or extraneous characters will be transmitted because of the break. 5 this bit is the stick parity bit. when bits 3, 4 and 5 are logic 1 the parity bit is transmitted and checked as logic 0. if bits 3 and 5 are 1 and bit 4 is logic 0 then the parity bit is transmitted and checked as logic 1. if bit 5 is a logic 0 stick parity is disabled. 4 this bit is the even parity select bit. when bit 3 is logic 1 and bit 4 is logic 0, an odd number of logic 1s is transmitted or checked in the data word bits and parity bit. when bit 3 is logic 1 and bit 4 is logic 1, an even number of logic 1s is transmitted or checked. 3 this bit is the parity enable bit. when bit 3 is logic 1, a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and stop bit of the serial data. (the parity bit is used to produce an even or odd number of 1s when the data word bits and the parity bit are summed). 2 this bit specifies the number of stop bits transmitted and received in each serial character. if bit 2 is logic 0, one stop bit is generated in the transmitted data. if bit 2 is logic 1 when a 5-bit word length is selected via bits 0 and 1, one and a half stop bits are generated. if bit 2 is a logic 1 when either a 6-, 7- or 8-bit word length is selected, two stop bits are generated. the receiver checks the first stop-bit only, regardless of the number of stop bits selected. 1:0 r/w these two bits specify the number of bits in each transmitted and received serial character. the encoding of bits 0 and 1 is as follows: value character length 00 5 bits 01 6 bits 10 7 bits 11 8 bits
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 153 - programmable baud generator HMS30C7210 uart can use only 3.692308mhz (pclk) that is made from 48mhz (cclk) clock at pmu. in addition, uart0 / uart1 can select 3.555556mhz (qclk) that is also made at pmu for smart card operation and the selection between 3.692308mhz and 3.555556mhz is performed by setting clocksel (bit4 of ucr). the output frequency of the baud generator is 16 x the baud [divisor # = (frequency input) / (baud rate x 16)]. two 8-bit latches store the divisor in a 16-bit binary format. these divisor latches must be loaded during initialization to ensure proper operation of the baud generator. upon loading either of the divisor latches, a 16-bit b aud counter is immediately loaded. baud rate table below provides decimal divisors to use with a frequency of 3.692308mhz. for baud rates of 38400 and below, the error obtained is minimal. the accuracy of the desired baud rate is dependent on the crystal frequency chosen. using a divisor of zero is not recommended. desired baud rate decimal divisor (used to generate 16 x clock) percent error difference between desired and actual 50 4608 - 110 2094 0.026 300 768 - 1200 192 - 2400 96 - 4800 48 - 9600 24 - 19200 12 - 38400 6 - 57600 4 115200 2 table 9-9 baud rate with decimal divisor at 3.92308mhz clock input
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 154 - 9.5.2.9 mcr(uart5 only) this register controls the interface with the modem or data set (or a peripheral device emulating a modem) and is valid at only uart5 because the onlu uart5 has the external modem pins. in addtion, mcr should not be accessed at uart0 and uart1, because uart0 and uart1 use this address for address of smr(smart card mode register). uxbase+0x10 7 6 5 4 3 2 1 0 0 0 0 loop - - rts uart5 only dtr uart5 only bits type function 7:5 r these bits are permanently set to logic 0 4 r/w this bit provides a local loop back feature for diagnostic testing of the uart. when bit 4 is set to logic 1, the following occur: the transmitter serial output (sout) is set to the marking (logic 1) state; the receiver serial input (sin) is disconnected; the output of the transmitter shift register is "looped back" into the receiver shift register input; the four modem control inputs (ncts, ndsr, ndcd and nri) are disconnected; and the two modem control outputs (ndtr and nrts) are internally connected to the four modem control inputs, and the modem control output pins are forced to their inactive state (high). on the diagnostic mode, data that is transmitted is immediately received. this feature allows the processor to verify the transmit- and received-data paths of the uart. in the diagnostic mode, the receiver and transmitter interrupts are fully operational. their sources are external to the part. the modem control interrupts are also operational, but the interrupts sources are now the lower four bits of the modem control register instead of the four modem control inputs. the interrupts are still controlled by the interrupt enable register. 3:2 - reserved 1 r/w this bit controls the request to send (nurts) output. bit 1 affects the nrts output in a manner identical to that described above for bit 0. 0 r/w this bit controls the data terminal ready (nudtr) output. when bit is set to logic 1, the ndtr output is forced to logic 0. when bit 0 is reset to logic 0, the ndtr output is forced to logic 1. note : the ndtr output of the uart may be applied to an eia inverting line driver (such as the ds1488) to obtain the proper polarity input at the succeeding modem or data set.
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 155 - 9.5.2.10 lsr this register provides status information to the cpu concerning the data transfer. uxbase+0x14 7 6 5 4 3 2 1 0 fifo err temt thre bi fe pe oe dr bits type function 7 r in the 16c450 mode this is always 0. in the fifo mode lsr7 is set when there is at least one parity error, framing error or break indication in the fifo. lsr7 is cleared when the cpu reads the lsr, if there are no subsequent errors in the fifo. 6 r this bit is the transmitter empty (temt) indicator. bit 6 is set to a logic 1 whenever the transmitter holding register (thr) and the transmitter shift register (tsr) are both empty. it is reset to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the transmitter fifo and register are both empty. 5 r this bit is the transmitter holding register empty (thre) indicator. bit 5 indicates that the uart is ready to accept a new character for transmission. in addition, this bit causes the uart to issue an interrupt to the cpu when the transmit holding register empty interrupt enable is set high. the thre bit is set to a logic 1 when a character is transferred from the transmitter holding register into the transmitter shift register. the bit is reset to logic 0 concurrently with the loading of the transmitter holding register. in the fifo mode this bit is set when the xmit fifo is empty; it is cleared when at least 1 byte is written to the xmit fifo. it may cause transmit error to write transmit fifos after polling this bit. if you want to use the transmit idle status to decides when to write the transmit fifos in polling mode, you had better to check the temp(bit6 of this register) rather than this bit. but, this bit can be used to check the timing to write transmit data in polling mode when fifo is disabled. this bit can also be used in the interrupt mode. 4 r this bit is the break interrupt (bi) indicator. bit 4 is set to logic 1 whenever the received data input is held in the spacing (logic 0) state for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). the bi indicator is reset whenever the cpu reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is revealed to the cpu when its associated character is at the top of the fifo. when break occurs, only one zero character is loaded into the fifo. the next character transfer is enabled after sin goes to the marking state and receives the next valid start bit. note : bits 1--4 are the error conditions that produce a receiver line status interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. 3 r this bit is the framing error (fe) indicator. bit 3 indicates that the received character did not have a valid stop bit. bit 3 is set to logic 1 whenever the stop bit following the last data bit or parity bit is detected as a logic 0 bit (spacing level). the fe indicator is reset whenever the cpu reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is revealed to the cpu when its associated character is at the top of the fifo. the uart will try to re-synchronize after a framing error. to do this it assumes that the framing error was due to the next start bit, so it samples this "start" bit twice and then takes in the "data". 2 r this bit is the parity error (pe) indicator. bit 2 indicates that the received data character does not have the correct even or odd parity, as selected by the even-parity-select bit. the pe bit is set to logic 1 upon detection of a parity error and is reset to logic 0 whenever the cpu reads the contents of the line status register. in the fifo mode, this error is associated with the particular character in the fifo it applies to. this error is revealed to the cpu when its associated character is at the top of the fifo. 1 r this bit is the overrun error (oe) indicator. bit 1 indicates that data in the receiver buffer register was not read by the cpu before the next character was transferred into the receiver buffer register, thereby destroying the previous character. the oe indicator is set to logic 1 upon detection of an overrun condition and reset whenever the cpu reads the contents of the line status register. if the fifo mode data continues to fill the fifo beyond the trigger level, an overrun error w ill occur only after t he fifo is full and t he next character has been completely received in the shift register. oe is indicated to the cpu as soon as it happens. the character in the shift register is overwritten, but it is not transferred to the fifo. 0 r this bit is the receiver data ready (dr) indicator. bit 0 is set to logic 1 whenever a complete incoming character has been received and transferred into the receiver buffer register or the fifo. bit 0 is reset to logic 0 by reading all of the data in the receiver buffer register or the fifo. some bits in lsr are automatically cleared when cpu reads the lsr register, so
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 156 - interrupt handling routine should be written that if once reads lsr, then keep the value through entire the routine because second reading lsr returns just reset value. 9.5.2.11 msr (uart5 only) this register provides the current state of the control lines from the modem (or peripheral device) to the cpu. in addition to this current-state information, four bits of the modem status register provide change information. these bits are set to logic 1 whenever a control input from the modem change state. they are reset to logic 0 whenever the cpu reads the modem status register. uxbase+0x18 7 6 5 4 3 2 1 0 dcd ri dsr cts ddcd teri ddsr dcts bits type function 7 r/o this bit is the complement of the data carrier detect (n udcd) input. if bit 4 of the mcr is set to a 1, this bit is equivalent to out2 in the mcr. note: whenever this bit changes its state, an interrupt is generated if the modem status interrupt is enabled. 6 r/o this bit is the complement of the ring indicator (nuring) input. if bit 4 of the mcr is set to a 1, this bit is equivalent to out1 in the mcr. note: whenever this bit changes its state from a high to a low state, an interrupt is generated if the modem status interrupt is enabled. 5 r/o this bit is the complement of the data set ready (nudsr) input. if bit 4 of the mcr is set to a 1, this bit is equivalent to dtr in the mcr. note: whenever this bit changes its state, an interrupt is generated if the modem status interrupt is enabled. 4 r/o this bit is the complement of the clear to send (nucts) input. if bit 4 (loop) of the mcr is set to a 1, this bit is equivalent to rts in the mcr. note: whenever this bit changes its state, an interrupt is generated if the modem status interrupt is enabled. 3 r/o this bit is the delta data carrier detect (nudcd) indicator. bit 3 indicates that the nudcd input to the chip has changed state since the last time it was read by the cpu. note: whenever bit 0, 1, 2 or 3 is set to logic 1, a modem status interrupt is generated. 2 r/o this bit is the trailing edge of ring indicator (teri) detector. bit 2 indicates that the nuring input to the chip has changed from a low to a high state. 1 r/o this bit is the delta data set ready (nudsr) indicator. bit 1 indicates that the nudsr input to the chip has changed state since the last time it was read by the cpu. 0 r/o this bit is the delta clear to send (nucts) indicator. bit 0 indicates that the nucts input to the chip has changed state since the last time it was read by the cpu.
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 157 - 9.5.2.12 scr this 8-bit read/write register does not control the uart in any way. it is intended as a scratchpad register to be used by the programmer to hold data temporarily. uxbase+0x1c 7 6 5 4 3 2 1 0 data bits type function 7:0 r/w temporary data storage 9.5.2.13 ucr (uart configuration register) to make the smart card interface mode set, smcarden and uarten are set to ?1? at the same time. if you use sir function, you must set siren and uart en bit at the same time. uxbase+0x30 7 6 5 4 3 2 1 0 - - smcarden uart0/1 only clocksel uart0/1 only sir loop back uart4 only full duplex force uart4 only siren uart4 only uarten bits type function 7:6 - reserved 5 r/w smart card interface mode set 0 = smart card interface disable 1 = smart card interface enable 4 r/w clock select 0 = 3.6864mhz 1 = 3.5712mhz 3 r/w sir loop-back test (uart1 only) 0 = sir loop-back test disable 1 = sir loop-back test enable. 2 r/w sir full-duplex force (uart1 only) 0 = half duplex. 1 = full duplex. 1 r/w sir enable (uart1 only) 0 = sir mode disable 1 = sir mode enable 0 r/w uart enable. 0 = uart disable (power-down), uart clock stop. 1 = uart enable.
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 158 - 9.5.3 fifo interrupt mode operation when the rcvr fifo and receiver interrupts are enabled (fcr 0 = 1, ier 0 = 1) rcvr interrupts occur as follows: ? the received data available interrupt will be issued to the cpu when the fifo has reached its programmed trigger level. it will be cleared as soon as the fifo drops below its programmed trigger level. ? the iir receive data available indication also occurs when the fifo trigger level is reached, and like the interrupt, it is cleared when the fifo drops below the trigger level. ? the receiver line status interrupt (iir-06), as before, has higher priority than the received data available (iir-04) interrupt. ? the data ready bit (lsr 0) is set as soon as a character is transferred from the shift register to the rcvr fifo. it is reset when the fifo is empty. when rcvr fifo and receiver interrupts are enabled, rcvr fifo time-out interrupts occurs as follows: ? a fifo time-out interrupt occurs if the following conditions exist: at least one character is in the fifo ? the most recent serial character received was longer than four continuous character times ago (if two stop bits are programmed, the second one is included in this time delay) ? the most recent cpu read of the fifo was longer than four continuous character times ago this will cause a maximum character received to interrupt issued delay of 160 ms at 300 baud with a 12-bit character. ? character times are calculated by using the rclk input, which is the internal signal of uart for a clock signal (this makes the delay proportional to the baud rate). ? when a time-out interrupt has occurred, it is cleared and the timer is reset when the cpu reads one character from the rcvr fifo. ? when a time-out interrupt has not occurred the time-out timer is reset after a new character is received or after the cpu reads the rcvr fifo. when the xmit fifo and transmitter interrupts are enabled (fcr 0 = 1, ier 1 = 1), xmit interrupts occurs as follows: ? the transmitter holding register interrupt (02) occurs when the xmit fifo is empty. it is cleared as soon as the transmitter holding register is written to (1 to 16 characters may be written to the xmit fifo while servicing this interrupt) or the iir is read. ? the transmitter fifo empty indications will be delayed 1 character time minus the last stop bit time whenever the following occurs: thre = 1 and there has not been at least two bytes at the same time in the transmit fifo since the last thre = 1. the first transmitter interrupt affect changing fcr0 will be immediate if it is enabled. character time-out and rcvr fifo trigger level interrupts have the same priority as the current received data available interrupt; xmit fifo empty has the same priority as the current transmitter holding register empty interrupt.
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 159 - 9.5.4 fifo polling mode operation when fcr is set to 1 and all bits of ier are clear to ?0?, uart is put to the fifo polled mode of operation. in this mode, user program will check receive and transmit status via line status register. cpu should do appropriate operation at each case of line status register.: ? lsr0 will be set as long as there is one byte in the receive fifo. ? lsr1~lsr4 will specify which error has occurred. character error status is handled the same way when in the interrupt mode, the iir is not affected since ier2 is ?0?. ? lsr5 will indicate when the transmit fifo is empty. ? lsr6 will indicate that both the transmit fifo and shift register are empty. ? lsr7 will indicate whether there are any errors in the receive fifo ? there are no trigger level reached or timeout condition indicated in the fifo polled mode.
amba peripherals (uart/sir) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 160 -
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 161 - 9.6 smart card interface a smart card interface is an extension of uart0/uart1 functions and supports the iso7816-3 standard. the switchover between normal uart function and smart card interface function is controlled by setting a uart configuration register (ucr) appropriately. if the uarten bit and smcarden bit of ucr are set simultaneously, the uart0 and uart1 are changed from normal uart mode to smart card interface mode. features ? card detect function(support the detection of case that card?s present and absent both) ? execute automatic contact activation and deactivation sequence. ? programmable clock cycle number setting of reset transition. ? built-in baud generator allows any bit rate to be selected. ? supports the asynchronous smart card communication. ? half-duplex data communication ? 8-bit data length ? support direct convention and indirect convention both ? parity bit generation and check ? transmit error signal (parity error) in receive mode ? error signal detection and automatic retransmission in transmission mode ? programmable extra guard time in transmission mode ? programmable waiting time cycle number. ? clock is enabled or disabled by register setting.
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 162 - 9.6.1 external signals uart0 and uart1 have smart card interface extension. at setting the smart card interface. enable bit of ucr, the signals table below are enabled at each uart / smart card interface. these smart card interface pin names are same as HMS30C7210 top pin names. to get the information about pin number of smart card interface signal at chip, refer to ?table 2-3 detail pin description?. pin name type description scpres[1:0] i card present signal this signal indicates that smart card is present(if this signal is logic ?1?) or not(if this signal is logic ?0?) in the slot. the card detect interrupt is generated at the rising edge(card is inserted) and falling edge(card is removed) both if the card detect interrupt is enable in ier scio[1:0] i/o data in/out signal from/to external smart card. this signal shall be fixed to logic ?0? at idle state. this signal is set in receive mode except transmitting data or parity error flag after contact activation starts scrst[1:0] o smart card reset signal. this signal is fixed to logic ?0? at idle state. on starting of contact activation sequence, this signal remains to logic ?0? waiting atr until the number of clock cycle set in the rtr. if the atr is not received until that number of clock cycle, crst is set to logic ?1? and waits for atr during the number of clock cycle set in the rtr once more. if there is no atr and the clock cycle elapses(the initialization of smart card fails) ,the contact deactivation start and the crst is et to logic ?0? scclk[1:0] o smart card clock signal. this clock starts when contact activation sequence starts(if cardinit and clken are set to ?1? in the smr). during the data transfer, 1-bit period is configured to the any number of cclk cycle as configured by divider value of dll/dlm and baudsel of smr if clken of smr is set to ?1?. if the baudsel is set to ?1?, 1-bit period is ?31 x divider-value?. if the baudsel is set to ?0?, 1-bit period is ?16 x divider value?. the cclk can be disabled by setting clken of smr to ?0?. in this case, cclk is fixed to ?0? if clkpol is ?0? and cc lk is fixed to ?0? if cclk is fixed to ?1? refer to figure 2-1. 208 pin diagram.
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 163 - 9.6.2 registers after uart0 and uart1 is set to the smart card interface mode, the register set is changed from the normal uart registers to smart card interface(sci) registers as blow. address name width default description 0x8005.4000 sci0base - - smart card interface 0 base 0x8005.5000 sci1base - - smart card interface 1 base rbr 8 0x00 receiver buffer register (dlab = 0, read only) thr 8 0x00 transmitter holding register (dlab = 0, write only) scixbase+0x00 dll 8 0x00 divisor latch least significant byte (dlab = 1, read/write) ier 8 0x00 interrupt enable register (dlab = 0, read/write) scixbase+0x04 dlm 8 0x00 divisor latch most significant byte (dlab = 1, read/write) iir 8 0x01 interrupt identification register (read only) scixbase+0x08 fcr 8 0x00 fifo control register (write only) scixbase+0x0c lcr 8 0x00 line control register(read/write) scixbase+0x10 smr 12 0x00 smart card mode register(read/write) scixbase+0x14 lsr 8 0x60 line status register(read only) scixbase+0x18 ssr 8 0xx0 smart card status register(read only) scixbase+0x1c scr 8 0x00 scratch register(read/write) scixbase+0x20 rtr 16 0x0190 reset timing register(read/write) scixbase+0x24 rnr 8 0x00 retransmit number register(read/write) scixbase+0x28 wtr 24 0x2580 waiting time register(read/write) scixbase+0x2c egr 8 0x00 smart card interface extra-guard time register(read/write). scixbase+0x30 ucr 6 0x00 uart configuration register(read/write) table 9-10 smart card interface register summary
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 164 - 9.6.2.1 rbr rbr is the receive buffer register and stores the data from serial input. this register is read-only and can be accessed when dlab(bit7 of line control register) is set to 0. scixbase+0x00 7 6 5 4 3 2 1 0 receive data bit 7 ~ receive data bit 0 bits type function 7:0 r receive byte that is received from serial input. 9.6.2.2 thr thr is the transmit buffer register and stores the data to be transmitted through serial output. this register is write-only and can be accessed when dlab(bit7 of line control register) is set to 0. scixbase+0x00 7 6 5 4 3 2 1 0 transmit data bit 7 ~ transmit data bit 0 bits type function 7:0 w transmit byte that is transmitted through serial output. 9.6.2.3 dll dll is the divisor latch least significant byte register and used to set the lower 8- bit of 16-bit baud-rate divisor value. scixbase+0x00 7 6 5 4 3 2 1 0 baud-rate divisor bit 7 ~ baud-rate divisor bit 0 bits type function 7:0 r/w lower 8-bit of 16-bit baud-rate divisor.
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 165 - 9.6.2.4 ier/dlm this register enables the five types of smart card interface interrupts. each interrupt can individually activate the interrupt (intuart) output signal. it is possible to totally disable the interrupt enable register (ier). similarly, setting bits of the ier register to logic 1 enables the selected interrupt(s). disabling an interrupt prevents it from being indicated as active in the iir and from activating the intuart output signal. all other system functions operate in their normal manner, including the setting of the line status and smart card status registers. table 13-6: summary of registers on page 13-10 shows the contents of the ier. details on each bit follow. scixbase+0x04 7 6 5 4 3 2 1 0 0 0 card det intr wait time intr tx ls intr rx ls intr tx empty intr data rdy intr bits type function 7 r/w 0 6 r/w 0 5 r/w enable the card detect (card insertion or removal) interrupt 4 r/w enables the initialization fail (atr is not received) interrupt or waiting time out interrupt 3 r/w enables the transmitter line status(parity error) interrupt when set to logic 1. 2 r/w enables the receiver line status (overrun/parity error) interrupt when set to logic 1. 1 r/w enables the transmitter holding register empty interrupt when set to logic 1. 0 r/w enables the received data available interrupt (and time-out interrupts in the fifo mode) when set to logic 1. 9.6.2.5 dlm dlm is the divisor latch most significant byte register and used to set the upper 8- bit of 16-bit baud-rate divisor value. scixbase+0x00 7 6 5 4 3 2 1 0 baud-rate divisor bit 15 ~ baud-rate divisor bit 8 bits type function 7:0 r/w upper 8-bit of 16-bit baud-rate divisor.
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 166 - 9.6.2.6 iir in order to provide minimum software overhead during data character transfers, the smart card interface prioritizes interrupts into five levels and records these in the interrupt identification register. the five levels of interrupt conditions are, in order of priority ? card detect (card insert or removal) ? receiver line status / transmitter line line status ? received data ready ? transmitter holding register empty ? card initialize fail / waiting time out bit4~bit0 of the iir are used to identify the highest priority interrupt that is pending. bit0 represents whether the interrupt is pending or not ? if bit0 is 1, no interrupt occurs now and if bit0 is 0, an interrupt is pending and the iir contents may be used as a pointer to the appropriate interrupt service routine. if two interrupts occurs simultaneously, bit4~bit0 of iir represents the higher priority number between these two interrupts. these bits represent the lower priority interrupt after cpu clears the higher priority interrupt. when the cpu accesses the iir, the uart freezes all interrupts and indicates the highest priority pending interrupt to the cpu. while this cpu access is occurring, the uart records new interrupts, but does not change its current indication until the access is complete. bit7~bit6 of iir are set to 1, when bit0 of fcr(fifo control register) is 1, otherwise these two bits are set to 0. scixbase+0x08 7 6 5 4 3 2 1 0 fifo en 0 intr id intr pend function bits type value prioriy level interrupt type interrupt source interrupt reset condition 00001 - none none - 01000 highest card detect status card insert or removal from/to slot reading the smart card status register 00110 second receiver line status overrun error or parity error reading the line status register 10110 second transmitter line status transmit parity error reading the line status register 00100 third receiver data avaliable receiver data available or trigger level reached reading the receiver buffer register or the fifo drops below the trigger level 10100 third character time- out indication no characters have been removed from or input to the rcvr fifo during the last 4 character times and there is at least 1 character in it during this time reading the receiver buffer register 00010 fourth transmitter holding register empty transmitter holding register empty reading the iir register (if source of interrupt) or writing into the transmitter holding register 4:0 r 00000 fifth wating timeout receive serial data waiting time is elapsed reading the smart card status register
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 167 - 10000 fifth card initialization fail the external smart card dose not give the atr during the initialization cycle reading the smart card status register 9.6.2.7 fcr this is a write-only register at the same location as the iir (the iir is a read-only register). this register is used to enable the fifos, clear the fifos and set the rcvr fifo trigger level. scixbase+0x08 7 6 5 4 3 2 1 0 rcvr trig level - - - xmit reset rcvr reset fifo en bits type function 7:6 w these two bits sets the trigger level for the rcvr fifo interrupt value rcvr fifo trigger level (bytes) 00 01 01 04 10 08 11 14 5:3 - reserved 2 w writing 1 resets the transmitter fifo counter logic to 0. the shift register is not cleared. the 1 that is written to this bit position is self-clearing 1 w writing 1 resets the receiver fifo counter logic to 0. the shift register is not cleared. the 1 that is written to this bit position is self-clearing 0 w writing 1 enables both the xmit and rcvr fifos. resetting fcr0 will clear all bytes in both fifos. when changing from fifo mode to 16c450 mode and vice versa, data is automatically cleared from the fifos. this bit must be a 1 when other fcr bits are written to or they will not be programmed
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 168 - 9.6.2.8 lcr the system programmer specifies the format of the asynchronous data communications exchange and set the divisor latch access bit via the line control register (lcr). the programmer can also read the contents of the line control register. the read capability simplifies system programming and eliminates the need for separate storage in system memory of the line characteristics. scixbase+0x0c 7 6 5 4 3 2 1 0 dlab set break stick parity even parity parity enable stopbit number word length select bits type function 7 this bit is the divisor latch access bit (dlab). it must be set high (logic 1) to access the divisor latches of the baud generator during a read or write operation. it must be set low (logic 0) to access the receiver buffer, the transmitter holding register or the interrupt enable register 6 this bit is the break control bit. this bit must be set to ?0? at the smart card interface mode it causes a break condition to be transmitted to the receiving uart. when it is set to logic 1, the serial output (sout) is forced to the spacing (logic 0) state. the break is disabled by setting logic 0. the break control bit acts only on sout and has no effect on the transmitter logic. note: this feature enables the cpu to alert a terminal in a computer communications system. if the following sequence is followed, no erroneous or extraneous characters will be transmitted because of the break. 5 this bit is the stick parity bit. this bit must be set to ?0? at the smart card interface mode when bits 3, 4 and 5 are logic 1 the parity bit is transmitted and checked as logic 0. if bits 3 and 5 are 1 and bit 4 is logic 0 then the parity bit is transmitted and checked as logic 1. if bit 5 is a logic 0 stick parity is disabled. 4 this bit is the even parity select bit. this bit must be set to ?1? at the smart card interface direct convention mode this bit must be set to ?0? at the smart card interface indirect convention mode when bit 3 is logic 1 and bit 4 is logic 0, an odd number of logic 1s is transmitted or checked in the data word bits and parity bit. when bit 3 is logic 1 and bit 4 is logic 1, an even number of logic 1s is transmitted or checked. 3 this bit is the parity enable bit. this bit must be set to ?1? at the smart card interface mode when bit 3 is logic 1, a parity bit is generated (transmit data) or checked (receive data) between the last data word bit and stop bit of the serial data. (the parity bit is used to produce an even or odd number of 1s when the data word bits and the parity bit are summed). 2 this bit specifies the number of stop bits transmitted and received in each serial character. this bit must be set to ?1? at the smart card interface mode. if bit 2 is logic 0, one stop bit is generated in the transmitted data. if bit 2 is logic 1 when a 5-bit word length is selected via bits 0 and 1, one and a half stop bits are generated. if bit 2 is a logic 1 when either a 6-, 7- or 8-bit word length is selected, two stop bits are generated. the receiver checks the first stop-bit only, r egardless of the number of stop bits selected. 1:0 r/w these two bits specify the number of bits in each transmitted and received serial character. these two bits must be ?11?(8-bit) at smart card interface mode the encoding of bits 0 and 1 is as follows: value character length 00 5 bits 01 6 bits 10 7 bits 11 8 bits
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 169 - programmable baud generator the uart0,1 / smart card interface contains a programmable baud generator that is capable of taking clock input (3.692308mhz or 3.555556mhz) and dividing it by any divisor from 2 to 2 16 -1. uart0,1/ smart card interface can select between 3.692308mhz and 3.555556hmz is performed by setting clocksel (bit4 of ucr).these divisor latches must be loaded during initialization to ensure proper operation of the baud generator. upon loading either of the divisor latches, a 16-bit baud counter is immediately loaded.the output frequency of the baud generator is 16 x the baud [divisor # = (frequency input) / (baud rate x 16)], if baudsel of smr is logic ?0? or 31 x the baud [divisor # = (frequency input) / (baud rate x 31)], if baudsel of smr is logic ?1?. the selection of baudsel depends on fi bits of atr in the smart card initialization process. if the forth bit of fi is logic ?0?, the baudsel shall be set to ?1?. if the forth bit of fi is logic ?1?, the baudsel shall be set to ?0?. two 8-bit latches store the divisor in a 16-bit binary format. baud rate table below provides decimal divisors to use with a frequency of 3.555556mhz and baudsel is logic ?1? or ?0?. using a divisor of zero is not recommended. desired baud rate decimal divisor (used to generate 16 x clock) percent error difference between desired and actual 9600 12 (baudsel = 1, fi = 0001) - 6400 18 (baudsel = 1, fi = 0010) - 4800 24 (baudsel = 1, fi = 0011) - 3200 36 (baudsel = 1, fi = 0100) - 2400 48 (baudsel = 1, fi = 0101) - 1920 60 (baudsel = 1, fi = 0110) - 6975 32 (baudsel = 0, fi = 1001) - 4650 48 (baudsel = 0, fi = 1010) - 3487 64 (baudsel = 0, fi = 1011) - 2325 96 (baudsel = 0, fi = 1100) 1744 128 (baudsel = 0, fi = 1101) table 9-11 baud rate with decimal divisor at 3.55556mhz clock input
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 170 - 9.6.2.9 smr (smart card mode register) this register controls the configuration when smart card interface mode is enabled. scixbase+0x10 11 10 9 8 disinit dirctlen rstval ioval 7 6 5 4 3 2 1 0 cardinit retranen datapol - datadir clkval clken baudsel bits type function 11 r/w smart card initialization sequence disable bit before data is transferred between smart card and sci, smart card contact must be activated and atr must be transferred from smart card to sci. if this bit is reset to ?0?, the above initialization sequence is performed as soon as cardinit (bit7 of this register) is set to ?1?. otherwise, the smart card skip the initialization sequence and ready for data transfer, as soon as cardinit is set to ?1?. 10 r/w direct control of cio/crst enable bit if this bit is set to ?1?, cio and crst pin are controlled directly by setting ioval(bit8 of this register) or rstval(bit9 of this register) in spite of current state of initialization sequence. if this bit is reset to ?0?, crst and cio pin?s levels are controlled only by state of initialization sequence. for example, crst is changed from ?0? to ?1? when sci is in smart card contact activation state, crst is fixed to ?1? when sci is in the data transfer state. 9 r/w reset bit(crst signal) level select bit when direct control of cio/crst is enabled this bit is used to indicate state of the crst pin when direct control of cio/crst is enabled (when dirctlen is set to ?1?). if this bit is reset to ?0? and dirctlen(bit10 of this register) is ?1? , the crst pin is fixed to logic ?0? state. otherwise, the cclk pin is fixed to logic ?1? state 8 r/w data bit(cio signal) level select bit when direct control of cio/crst is enabled this bit is used to indicate state of the cio pin when direct control of cio/crst is enabled (when dirctlen is set to ?1?). if this bit is reset to ?0? and dirctlen(bit10 of this register) is ?1? , the cio pin is fixed to logic ?0? state. otherwise, the cclk pin is fixed to logic ?1? state 7 r/w smart card initialization bit. the contact initialization sequence starts when this bit and carden bit of ucr is set to ?1? after card initialization sequence is successfully finished, the smart card interface can exchange the data with the external card. this bit shall be reset to ?0? to make the contact deactivation sequence start at the end of data transfer with the external card this bit is also reset to ?0? automatically in the case that the external card does not give the atr and initialization is failed. at this case, the contact deactivation sequence starts automatically 6 r/w retransmit enable bit this bit is set to enable the retransmission of parity-errored data at transmitter operation and the transmission of error flag at receiver operation if this bit is reset to ?0?, the function of error flag transmission and data retransmission is disable 5 r/w data bit(cio signal) polarity bit if this bit is reset to ?0?, the logic 1 level of cio corresponds to state z and the logic 0 level to state a. otherwise, the logic 1 level corresponds to state a and the logic 0 level to state z this bit shall be reset to ?1? at direct convention and this bit shall be set to ?1? at indirect convention 4 - reserved for normal uart function. 3 r/w data bit(cio signal) direction select bit when this bit is reset to ?0?, the data frame transfer is performed in lsb-first order. otherwise, the data frame is performed in msb-first order. this bit shall be reset to ?1? at direct convention and this bit shall be set to ?1? at indirect convention 2 r/w cclk level select bit when cclk is disabled this bit is used to indicate state of the cclk pin when cclk is not enabled (when clken is reset to ?0?). if this bit is reset to ?0? and clken(bit1 of this register) is ?0? , the cclk pin is fixed to logic ?0? state. otherwise, the cclk pin is fixed to logic ?1? state 1 r/w cclk enable bit this bit is used to enable or disable the cclk pin. if this bit is reset to ?0?, cclk pin is disabled and fixed to logic level as indicated to clkvall(bit2 of this register) otherwise, cclk pin is enabled and clock signal is transferred
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 171 - to cclk pin 0 r/w baud select bit the output frequency of the baud generator is 16 x the baud [divisor # = (frequency input) / (baud rate x 16)], this bit is logic ?0?. 31 x the baud [divisor # = (frequency input) / (baud rate x 31)], if this bit is logic ?1?.
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 172 - 9.6.2.10 lsr this register provides status information to the cpu concerning the data transfer. scixbase+0x14 7 6 5 4 3 2 1 0 fifo err temt thre txpe - pe oe dr bits type function 7 r in the 16c450 mode this is always 0. in the fifo mode lsr7 is set when there is at least one parity error in the fifo. lsr7 is cleared when the cpu reads the lsr, if there are no subsequent errors in the fifo. 6 r this bit is the transmitter empty (temt) indicator. bit 6 is set to a logic 1 whenever the transmitter holding register (thr) and the transmitter shift register (tsr) are both empty. it is reset to logic 0 whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to one whenever the transmitter fifo and register are both empty. 5 r this bit is the transmitter holding register empty (thre) indicator. bit 5 indicates that the uart/smart card interface is ready to accept a new character for transmission. in addition, this bit causes the uart/smart card interface to issue an interrupt to the cpu when the transmit holding register empty interrupt enable is set high. the thre bit is set to a logic 1 when a character is transferred from the transmitter holding register into the transmitter shift register. the bit is reset to logic 0 concurrently with the loading of the transmitter holding register. in the fifo mode this bit is set when the xmit fifo is empty; it is cleared when at least 1 byte is written to the xmit fifo. 4 r- this bit is transmitter parity error (txpe) indicator. if retranen bit of smr is set to ?1?, this bit is set to logic 1 in the case that the external card transmits the parity error flag of received data and the interface device re-transmit the errored data frame for the times of the rnr value, but parity will not be removed and the external card transmit error flag also if retranen bit of smr is set to ?0?, this bit is set to ?1? as soon as the parity error flag is received. this bit is reset whenever the cpu reads the contents of the line status register. in the fifo mode this error is associated with the particular character in the fifo it applies to. this error is revealed to the cpu when its associated character is at the top of the fifo. note: bits 4 is the error conditions that produce a transmitter line status interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. 3 - this bit is reserved at smart card interface mode 2 r this bit is the receive parity error (pe) indicator. if retr anen bit of smr is set to ?0?, this bit is set to ?1? upon detection of a parity error. if retranen bit of smr is set to ?1?, the interface detects the received parity error and transmit the error flag and the external card retransmits the data. if the number of receiving re-transferred data from the external card is same to the value saved in the rnr but error is not corrected, this pe bit is set to logic 1. this bit is reset to logic 0 whenever the cpu reads the contents of the line status register. in the fifo mode, this error is associated with the particular character in the fifo it applies to. this error is revealed to the cpu when its associated character is at the top of the fifo. note: bits 2-1 is the error conditions that produce a receiver line status interrupt whenever any of the corresponding conditions are detected and the interrupt is enabled. 1 r this bit is the overrun error (oe) indicator. bit 1 indicates that data in the receiver buffer register was not read by the cpu before the next character was transferred into the receiver buffer register, thereby destroying the previous character. the oe indicator is set to logic 1 upon detection of an overrun condition and reset whenever the cpu reads the contents of the line status register. if the fifo mode data continues to fill the fifo beyond the trigger level, an overrun error w ill occur only after t he fifo is full and t he next character has been completely received in the shift register. oe is indicated to the cpu as soon as it happens. the character in the shift register is overwritten, but it is not transferred to the fifo. 0 r this bit is the receiver data ready (dr) indicator. bit 0 is set to logic 1 whenever a complete incoming character has been received and transferred into the receiver buffer register or the fifo. bit 0 is reset to logic 0 by reading all of the data in the receiver buffer register or the fifo. some bits in lsr are automatically cleared when cpu reads the lsr register, so interrupt handling routine should be written that if once reads lsr, then keep the value through entire the routine because second reading lsr returns just reset value.
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 173 - 9.6.2.11 ssr (smart card status register) this register provides the additional state of the smart card interface to the cpu. in addition to this current-state information, three bits of the smart card status register provide interrupt information except tx /rx data interrupt (these information is in the lsr). these bits are set to logic 1 whenever a interrupt condition occurs e. they are reset to logic 0 whenever the cpu reads the modem status register. scixbase+0x18 7 6 5 4 3 2 1 0 - - - - retrans_to waittimeout initfail cardpre bits type function 7 this bit is reserved at smart card interface mode 6 this bit is reserved at smart card interface mode 5 this bit is reserved at smart card interface mode 4 this bit is reserved at smart card interface mode 3 this bit indicate the retransmit of error data is timeout when retranen(bit 6 of smr) is set to 1. this bit is set to ?1? in the case that the interval between start leading edge of the retransmitted data frame sent by the external card and the start leading edge of previous error data frame (sent by the card but parity error is detected by sci) exceeds the waiting time value of wtr register. this bit is reset to ?0? whenever the cpu reads the contents of the smart card status register 2 this bit indicates that the waiting time out is occurs. this bit is set to ?1? in the case that the interval between start leading edge of the data frame sent by the external card and the start leading edge of previous data frame (sent either by the card or by the interface device) exceeds the waiting time value of wtr register. this bit is reset to ?0? whenever the cpu reads the contents of the smart card status register 1 this bit is set to ?1? when the initialization sequence is fail and the atr from the external card is not received. as soon as this bit is set to ?1? and card initialization is failed, the interface device starts the contact deactivation sequence and the cardinit bit of smr is reset to ?0? automatically. this bit is reset to ?0? whenever the cpu reads the contents of the smart card status register 0 - this bit is set to ?1? when the external card is inserted and cardpresent pin is logic ?1? this bit is reset to ?1? when the external card is removed and cardpresent pin is logic ?0? the change of this bit or cardpresent pin triggers the carddet interrupt 9.6.2.12 scr this 8-bit read/write register does not control the uart/smart card interface in any way. it is intended as a scratchpad register to be used by the programmer to hold data temporarily. scixbase+0x1c 7 6 5 4 3 2 1 0 data bits type function 7:0 r/w temporary data storage
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 174 - 9.6.2.13 rtr (reset timing register) on starting of contact activation sequence, the crst remain to logic ?0? waiting atr until the number of clock cycle set in the rtr register. if the atr is not received until that number of the clock cycle, crst is set to logic ?1? and waits for atr during the number of clock cycle set in the rtr once more. if there is no atr and the clock cycle elapses(the initialization of smart card fails) ,the contact deactivation start and the crst is set to logic ?0? the minimum value of this register is 200,so this register must be set greater than 200. scixbase+0x20 16 15 ? 1 0 clock cycle number bits type function 15:0 r/w the clock(cclk) cycle number that is used to count the clock number during which the interface device waits for atr. 9.6.2.14 rnr (retransmit number register) this register value identifies the number of retransmission before tx/rx line status interrupt is activated and line status error occurs. the tx/rx line status interrupt occurs if the line status error is not cleared after the re-transmission of the times that is saved in this register. if the value of this register is set to ?0?, no error flag is transmitted even though the smart card interface receives the error-ed data frame and rx line error status interrupt occurs immediately. if the interface device is transmit mode and receives the error flag, the interface device does not re-transmit the error-ed data frame and activates the tx line status error interrupt immediately. scixbase+0x24 7 6 5 4 3 2 1 0 re-transmission number bits type function 7:0 r/w retransmission number of errored data, before tx/rx line status interrupt occurs.
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 175 - 9.6.2.15 wtr (waiting time register) in the case that the interval between start leading edge of the data frame sent by the external card and the start leading edge of previous data frame (sent either by the card or by the interface device) exceeds the waiting time value of wtr register, the waiting timeout interrupt occurs scixbase+0x28 23 22 ? 1 0 the number of data bit period bits type function 23:0 r/w waiting timeout value that is number of 1-bit data period 9.6.2.16 egr (extra guard-time register) this register value set the number of bit ?period that follows the 12-bit data frame, and from 0 to 254. if egr value is 255, the minimum delay between the start edges of two consecutive data frame is reduce to 11-bit period. scixbase+0x2c 23 22 ? 1 0 the number of data bit period bits type function 23:0 r/w extra guard-time that follow the 12-bit character data frame
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 176 - 9.6.2.17 ucr (uart configuration register) to make the smart card interface mode set, smcarden and uarten are set to ?1? at the same time. uxbase+0x30 7 6 5 4 3 2 1 0 - - smcarden clocksel sir loop back uart4 only full duplex force uart4 only siren uart4 only uarten bits type function 7:6 - reserved 5 r/w smart card interface mode set 0 = smart card interface disable 1 = smart card interface enable (if you use smart card interface function, you must set this bit with uarten bit at the same time). 4 r/w clock select 0 = 3.6864mhz 1 = 3.5712mhz 3 r/w sir loop-back test (uart1 only) 0 = sir loop-back test disable 1 = sir loop-back test enable. 2 r/w sir full-duplex force (uart1 only) 0 = half duplex. 1 = full duplex. 1 r/w sir enable (uart1 only) 0 = sir mode disable 1 = sir mode enable (if you use sir function, you must set this bit with uarten bit at the same time). 0 r/w uart enable. 0 = uart disable (power-down), uart clock stop. 1 = uart enable.
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 177 - 9.6.3 smart card interface operation flow chart before transmitting or receiving data, the smart card interface and smart card must be initialized as described in figure 9-4, after performing contact initialization and atr receiving, the configuration of smart card interface must be change to meet the condition of atr as describe in figure 9-5. set carddet intr enabled at ier card det intr occur ? no yes setuarten,smcarden, clocken at ucr set ier, fcr,lcr set rtr,rnr set smr and set cardinit to start initialization init fail intr occur ? no initialization fail no rx line status or waiting timeout intr? yes receiving atr fail no rcv data ready intr? yes read rhr or rx-data fifo yes smart card initialization sequence data receive sequence all data received? yes atr receive done no set carddet intr enabled at ier card det intr occur ? no yes setuarten,smcarden, clocken at ucr set ier, fcr,lcr set rtr,rnr set smr and set cardinit to start initialization init fail intr occur ? no initialization fail no rx line status or waiting timeout intr? yes receiving atr fail no rcv data ready intr? yes read rhr or rx-data fifo yes smart card initialization sequence data receive sequence all data received? yes atr receive done no figure 9-2 card initialization and receiving atr flow chart
amba peripherals (smart card interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 178 - set wtr, egr,dll/dlm and smr as atr execute tx oper ? no yes write thr or tx data fifo tx oper done tx line status intr ? yes tx opr fail tx data empty intr ? yes all data is transmitted? yes no no execute data receive sequence in privious figure set wtr, egr,dll/dlm and smr as atr execute tx oper ? no yes write thr or tx data fifo tx oper done tx line status intr ? yes tx opr fail tx data empty intr ? yes all data is transmitted? yes no no execute data receive sequence in privious figure figure 9-3 data transmission and reception flow chart
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 179 - 9.7 synchronous serial interface (ssi) the HMS30C7210 includes two ssis (synchronous serial interface) that are amba slave blocks connecting to the apb. the ssi is a master or slave interface that enables synchronous serial communication with an external slave or master peripheral. the ssi only supports a motorola spi-compatible interface that features full-duplex, three-wire synchronous transfers and programmable clock polarity and phase. in both master and slave configurations, the ssi performs parallel-to-serial conversion on data written to a 8-bit wide, 8-location deep transmit fifo and serial- to-parallel conversion on received data, buffering it in a 8-bit wide, 8-location deep receive fifo. figure 9-23 shows a block diagram of the ssi. features ? master or slave operation ? motorola spi-compatible synchronous serial interface ? programmable transfer clock bit rate, clock polarity and phase ? separate transmit and receive fifo buffers, 8 bits wide, 8 locations deep ? 8-bit data frame size ? full-duplex, 3-wire synchronous transfers ? independent masking of transmit fifo, receive fifo and receive overrun interrupts ? internal loop-back test mode available sclkout ssprxd ssptxd sclksel sclkin sspclkdiv pd[7:0] register block transmit/ receive logic rx fifo tx fifo clock divider interrupt generator bnres psel pstb pwrite bclk paddr txfdata[7:0] txsdata[7:0] rxfdata[7:0] rxsdata[7:0] ssprxintr sspintr ssptxintr ssprorintr roris ris tis sfrmin sfrmout figure 9-23. ssi block diagram
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 180 - 9.7.1 register description the ssibase is 0x8005a000 for ssi0 and 0x8005b000 for ssi1. note marked ?-? bits in the following tables are reserved bits and return zeros on reads. 9.7.1.1 sspcr0 (control register 0) ssibase + 0x00 (initial value 8?bxxx0_0000) 7 6 5 4 3 2 1 0 - - - gsel sdir sph spo ms bits type function 4 r/w nsfrmin/out select from gpio 0 : nsfrmin = 0 (sdir=0), gpio pin =nsfrmout (sdir=1) 1 : nsfrmin = gpio pin (sdir=0), gpio pin = nsfrmout (sdir=1) 3 r/w sclkin/out nsfrmin/out direction the reset value of sdir bit is zero (input). if ms bit is used to indicate the direction instead of sdir, bus conflicts may occur. 0 = input (sclkin, nsfrmin input) 1 = output (sclkout, nsfrmout output) 2 r/w sclkin input phase (ms=1) and/or sclkout output phase (ms=0) 0 = sclkin/out starts toggling at the middle of the data transfer. 1 = sclkin/out start toggling at the beginning of the data transfer. 1 r/w sclkin input polarity (ms=1) and/or sclkout output polarity (ms=0) 0 = the inactive state of sclkin/out is low. 1 = the inactive state of sclkin/out is high. 0 r/w master or slave select 0 = configured as a master 1 = configured as a slave
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 181 - 9.7.1.2 sspcr1 (control register 1) ssibase + 0x04 (initial value 8?bxxxx_0000) 7 6 5 4 3 2 1 0 - - - - sse rorie tie rie bits type function 3 r/w sse : ssi enable 0 = ssi disabled 1 = ssi enabled 2 r/w rorie : rx fifo over-run interrupt enable 0 = receive over-run interrupt disabled writing ?0? to this bit will also clear roris bit in sspicr 1 = receive over-run interrupt enabled 1 r/w tie : tx fifo interrupt enable 0 = tx fifo interrupt disabled 1 = tx fifo interrupt enabled 0 r/w rie : rx fifo interrupt enable 0 = rx fifo interrupt disabled 1 = rx fifo interrupt enabled 9.7.1.3 sspdr (data register) sspdr is the data register and is 8-bit wide. when sspdr is read, the entry in the receive fifo pointed to by the current fifo read pointer is accessed. when sspdr is written to, the entry in the transmit fifo pointed to by the write pointer is written to. ssibase + 0x08 (initial value 8?bxxxx_xxxx) 7 6 5 4 3 2 1 0 fifo7 fifo6 fifo5 fifo4 fifo3 fifo2 fifo1 fifo0 bits type function 7:0 r/w transmit/receive fifo read ? receive fifo write ? transmit fifo
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 182 - 9.7.1.4 sspsr (status register) ssibase + 0x0c (read-only register) 7 6 5 4 3 2 1 0 - - - bsy rff rne tnf tfe bits type function 4 r bsy : ssi busy 0 = ssi is idle or is transferring msb (fifo[7]) 1 = ssi is transferring frame fifo[6:0], not msb 3 r rff : receive fifo full 0 = rx fifo is not full 1 = rx fifo is full 2 r rne : receive fifo not empty 0 = rx fifo is empty 1 = rx fifo is not empty 1 r tnf : transmit fifo not full 0 = tx fifo is full 1 = tx fifo is not full 0 r tfe : transmit fifo empty 0 = tx fifo is not empty 1 = tx fifo is empty 9.7.1.5 sspcsr (clock scale register) sspcsr specifies the division factor by which the input bclk should be internally divided to make sclkout. ssibase + 0x10 (initial value 8?bxxxx_xxx0) 7 6 5 4 3 2 1 0 csr7 csr6 csr5 csr4 csr3 csr2 csr1 csr0 bits type function 7:0 r/w clock divisor scale should be an even number from 2 to 254 on writes. the least significant bit always returns zero on reads.
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 183 - 9.7.1.6 sspiir/sspicr (interrupt status/clear register) ssibase+0x14 (initial value 8?bxxxx_x000) 7 6 5 4 3 2 1 0 - - - - - roris tis ris bits type function 2 r/w roris : rx over-run interrupt status/clear register write 0 ? no effect write 1 ? clears this bit read 0 ? no rx over-run interrupt state read 1 ? rx over-run interrupt state writing 0 to rorie bit will also clear roris bit 1 r/w tis : tx interrupt status/clear register write 0 ? no effect write 1 ? clears this bit read 0 ? no tx interrupt state read 1 ? tx interrupt state 0 r/w ris : rx interrupt status/clear register write 0 ? no effect write 1 ? clears this bit read 0 ? no rx interrupt state read 1 ? rx interrupt state
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 184 - 9.7.1.7 sspfent (fifo entry number) ssibase + 0x18 (initial value 8?b0000_0000) 7 6 5 4 3 2 1 0 txent3 txent2 txent1 txent0 rxent3 rxent2 rxent1 rxent0 bits type function 7:4 r the number of valid entries in transmit fifo 3:0 r the number of valid entries in receive fifo 9.7.1.8 sspient (fifo entry interrupt number) ssibase + 0x1c (initial value 8?b0100_0100) 7 6 5 4 3 2 1 0 txient3 txient2 txient1 txient0 rxient3 rxient2 rxient1 rxient0 bits type function 7:4 r/w this register is reset to 0x4 and enables programmers to specify the number at which tis is set. 0xf ? 0x9 : tis is never set. 0x8 : tis is always set 0x7 ? 0x0 : tis is set when txent <= txient tis is not set when txent > txient 3:0 r/w this register is reset to 0x4 and enables programmers to specify the number at which ris is set. 0xf ? 0x9 : ris is never set. 0x8 ? 0x1 : ris is set when rxent >= rxient ris is not set when rxent < rxient 0x0 : ris is always set
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 185 - 9.7.1.9 ssptcer (test clock enable register) ssibase + 0x40-0x7c (initial value 8?b0000_0000) 7 6 5 4 3 2 1 0 tce7 tce6 tce5 tce4 tce3 tce2 tce1 tce0 bits type function 7:0 r/w test clock enable. actually 0-bit register write : when in registered clock mode, a test clock enable is produced only when this register is accessed read : when in registered clock mode, a test clock enable is produced only when this register is accessed returned value is always 8?b0000_0000 ssptcer has a multiple word space in the register address map to allow for the generation of multiple test clock enable pulses. 9.7.1.10 ssptcr (test control register) ssibase + 0x80 (initial value 8?bxxx0_0000) 7 6 5 4 3 2 1 0 - - - tinpsel treset regclk tclken testen bits type function 4 r/w tinpsel : test input select 0 = normal input is selected 1 = values from ssptisr is multiplexed into input 3 treset : test reset 0 = no test reset 1 = nssprst is asserted throughout the ssi except for test registers 2 regclk : registered mode clock see table below. 1 r/w tclken : test clock enable see table below. 0 r/w testen : test mode enable 0 = normal operating mode is selected 1 = test mode is selected see table below. regclk tclken testen sclkin/out bclk 1 1 1 registered clock registered clock 1 0 1 registered clock bclk 0 1 1 divided clock registered clock 0 0 1 strobe clock bclk x x 0 divided clock bclk registered clock : generates a test clock enable on an apb access only to the ssptcer strobe clock : generates a test clock enable on every amba apb access to the block divided clock : generates a normal mode sclkin/out by dividing bclk
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 186 - 9.7.1.11 ssptmr (test mode register) ssibase + 0x84 (initial value 8?bxxxx_xx00) 7 6 5 4 3 2 1 0 - - - - - - nibmode lbm bits type function 1 r/w nibble mode counter 0 = normal csr counter (csc) mode 1 = 7-bit csr counter is partitioned into two nibbles (3-bit, 4-bit) and decrements by 0x11 on successive clocks 0 r/w loop back mode 0 = normal serial port operation 1 = output of transmit serial shifter is connected to input of receive serial shifter internally 9.7.1.12 ssptisr (test input stimulus register) ssptisr provides test mode stimulus for the sclkin and sclkin input to the ssi. when tinpsel bit in the s sptcr register is 1, the values in the ssptisr are routed to the internal lines. ssibase + 0x88 (initial value 8?bxxxx_xxxx) 7 6 5 4 3 2 1 0 - - - - - ntsfrmin tsclkin tssprxd bits type function 2 r/w test nsfrmin input for nsfrmin pin 1 r/w test sclkin input for sclkin pin 0 r/w test ssprxd input for ssprxd pin
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 187 - 9.7.1.13 ssptocr (test output capture register) ssibase + 0x8c (initial value 8?bx000_0010) 7 6 5 4 3 2 1 0 - rorintr txintr rxintr intr ssptxd nsfrmout sclkout bits type function 6 r rorintr : returns the status of ssprorintr ssprorintr is generated by roris anded with rorie 0 = ssprorintr pin is driven to logic 0 1 = ssprorintr pin is driven to logic 1 5 r txintr : returns the status of ssptxintr ssptxintr is generated by tis anded with tie 0 = ssptxintr pin is driven to logic 0 1 = ssptxintr pin is driven to logic 1 4 r rxintr : returns the status of ssprxintr ssprxintr is generated by ris anded with rie 0 = ssprxintr pin is driven to logic 0 1 = ssprxintr pin is driven to logic 1 3 r intr : returns the status of sspintr 0 = sspintr pin is driven to logic 0 1 = sspintr pin is driven to logic 1 2 r ssptxd : returns the status of ssptxd 0 = ssptxd pin is driven to logic 0 1 = ssptxd pin is driven to logic 1 1 r nsfrmout : returns the status of nsfrmout 0 = nsfrmout pin is driven to logic 0 1 = nsfrmout pin is driven to logic 1 0 r sclkout : returns the status of sclkout 0 = sclkout pin is driven to logic 0 1 = sclkout pin is driven to logic 1
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 188 - 9.7.1.14 ssptccr (test clock counter register) this register provides observation for the clock scale counter. the counter is 7-bit, free-running, down counter that operates on bclk, in normal mode of operation. it can be configured as two nibbles and decremented by test clocks in test mode through ssptmr and ssptcr registers. the seven most significant bits programmed in the 8-bit sspcsr register form the reload value for this counter. the counter reloads when it reaches 0x01. ssibase + 0x90 (initial value 8?bx000_0001) 7 6 5 4 3 2 1 0 - csc6 csc5 csc4 csc3 csc2 csc1 csc0 bits type function 6:0 r this bits return the current count of the clock scale counter
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 189 - 9.7.2 overview the ssi performs parallel-to-serial conversion on data to transmit to an external device and serial-to-parallel conversion on data to receive from an external device. the transmit and receive paths are buffered with internal fifo memories allowing up to eight 8-bit values to be stored independently. the ssi includes a programmable bit rate clock divider to generate the serial output clock sclkout from the bus clock bclk when configured as a master. the frequency of bclk is 30mhz (fclk/2) and it is divided, through the sspcsr register, by a factor of from 2 to 254 in steps of two. when configured as a slave, the sclkin clock is provided by an external master and used to time its transmission and reception sequences. there are four interrupts generated by the ssi and three of these are individual, maskable, active high interrupts: ssptxintr : active when the number of valid entries in the transmit fifo is equal to or less than the predetermined number specified by rxient. ssprxintr : active when the number of valid entries in the receive fifo is equal to or more than the predetermined number specified by txient. ssprorintr : active when the receive fifo is already full and an additional data frame is received. above three individual interrupts are also combined into a single output interrupt signal (sspintr). the combined sspintr is asserted if any of the three individual interrupts are asserted and enabled. there are registers and logic for functional block verification, and manufacturing or production test using tic vectors. test re gisters should not be read or written to during normal use.
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 190 - 9.7.3 operational description the ssi is reset by nssprst and it is generated by the global reset signal bnres or the test reset signal in ssi test mode. an external reset controller must use bnres to reset the whole ssi including test logic. the test reset signal resets ssi registers except for test mode registers. following the reset, the ssi is disabled and should be configured in this state. control register sspcr0 need to be programmed to decide several operation parameters. gsel bit determines whether nsfrmin signal from the gpio is used in slave mode. if gsel bit is cleared, the ssi regards nsfrmin signal as zero and transfers are synchronized only with sclkin clock signal. if gsel bit is set, nsfrmin signal from a gpio pin is used to indicate valid sclkin period and transfers are synchronized with sclkin when nsfrmin is zero. in master mode, gsel bit has no effects and nsfrmout signal to a gpio pin is always valid. sdir bit is used to determine the direction of nsfrmin/out and sclkin/out pins in the gpio. when sdir bit is set, the direction is output and nsfrmout and sclkout signals go out through gpio pins. ms bit configures the ssi as a master or slave and sph and spo bits determine clock phase and polarity respectively. when master, the bit rate requires the programming of the clock scale register sspcsr. the sspcr1 has ssi enable (sse) and interrupts enable bits. w hen disabled in master mode, sclkout is forced to low (spo=0) or high (spo=1), nsfrmout to high, and ssptxd to low. when disabled in slave mode, sclkin, nsfrmin and ssprxd has no meanings and ssptxd is set to low. once enabled, transmission and reception of data begins on transmit (ssptxd) and receive (ssprxd) pins. note : when nsfrmin/out signal from/to a gpio pin is not connected, sdir and spo bits in a master should be configured before a slave is enable. otherwise, the transition of sclkout generated by setting cdir and/or spo in the master may cause the slave into malfunctioning. in this case, the recommended sequence of register setup is following. sspcr0 regi ster in a master should be configured first. then sspcr0 in a slave is set and a slave ssi is enabled. the master is enabled last. once the bottom entry of the transmit fifo in a master contains data, nsfrmout is active to low to indicate valid data frame and the msb of the 8-bit data frame is shifted out onto the ssptxd pin. then, sclkout pin starts running and the serial data bit through ssprxd is captured in the receive fifo. after the lsb of the current data frame is shifted out, if there is no more valid entry in the transmit fifo, sclkout stops toggling and nsfrmout is inactive to indicate the completion of the transfer. otherwise, any valid entries in the transmit fifo enables another data frame transfer to be continued without delay. figure 9-7. shows the frame format for a single frame and figure 9-8. shows the timing diagram when back to back frames are transmitted. if the receive fifo is already full and the transmit fifo is not empty in master mode, a transfer will start but this transfer will cause receive overrun interrupt condition. in this case, a transmit data frame is read from the transmit fifo and transferred, and a received data frame is overwritten in the receive serial shift buffer normally. but, data in the receive serial buffer will not be stored in the receive fifo, if the receive fifo is still full until this transfer finishes. if rorie bit is set for the receive overrun condition, ssprorintr will signal and further data frame will not start until roris bit is cleared. in case of slave mode, the operation is the same except that a data frame starts with sclkin from external device. if the transmit fifo is already empty and another data frame is request in slave mode, a transmit fifo underrun condition occurs. the receive fifo operates normally but
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 191 - transmit fifo transfers the same data frame as in the previous transfer. this condition cannot occur in master mode. in this version of ssi, there is not an assigned interrupt for this case. if cpu writes data to the transmit fifo that is already full, the valid entries (from the oldest entry that was written) in the fifo can be overwritten. to detect this erroneous state, txent bits can be read. if txent[3:0] is in the range of from 0x9 to 0xf, the number of lost entries is txent - 0x8. msb msb msb msb q lsb lsb lsb lsb q sspclkin/out (spo=0) sspclkin/out (spo=1) ssptxd (sph=0) master out, slave in ssptxd (sph=1) master out, slave in ssprxd (sph=1) master in, slave out ssprxd (sph=1) master in, slave out nsfrmin/out (from/to gpio) figure 9-24. transfer format (single transfer)
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 192 - msb msb lsb lsb sspclkin/out (spo=0) sspclkin/out (spo=1) ssptxd/ssprxd (sph=0) ssptxd/ssprxd (sph=1) lsb lsb msb msb nsfrmin/out (from/to gpio) 0 figure 9-25. transfer format (back to back transfer) if cpu reads data from the receive fifo that is already empty, invalid entries in the receive fifo can be read. by reading rxent bits, this erroneous state can be detected. if rxent[3:0] is in the range of from 0x9 to 0xf, the number of entries that has been read by mistake is 0x10 ? rxent. note this version of the ssi supports neither mu lti-master nor multi- slave configurations.
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 193 - 9.7.4 ssi ac timming figure 9-4 ssi ac timing sspclkin/out ssptxd ssprxd t od t oh t is t ih sym bol description min. max to d o u tp u t d e la y fro m c lo c k to t x d - 3ns to h o u tp u t h o ld tim e fro m c lo c k to t x d 1ns - tis rxd input setup tim e 3ns - tih rxd input hold tim e 0.5ns -
amba peripherals (synchronous serial interface) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 194 -
amba peripherals (smc controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 195 - 9.8 smc controller this smartmedia? card controller is an advanced microcontroller bus architecture (amba) compliant system-on-a-chip peripheral providing an interface to industry- standard smartmedia? flash memory card. a channel has 8 control signal outputs and 8 bits of bi-directional data ports. features ? one 3.3v smartmedia support ? 4mb to 128mb media (both flash and mask rom type) ? interrupt mode support when erase/write operation is finished ? unique id smartmedia support ? multi-page (up to 32 pages) access (read/write) ? hardware 3byte ecc generation & check (software correctable). ? marginal timing operation settable.
amba peripherals (smc controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 196 - 9.8.1 external signals pin name type description smd [7:0] i/o smart media card (ssfdc) 8bit data signals nsmwp o smart media card (ssfdc) write protect nsmwe o smart media card (ssfdc) write enable smale o smart media card (ssfdc) address latch enable smcle o smart media card (ssfdc) command latch enable nsmcd i smart media card (ssfdc) card detection signal nsmce o smart media card (ssfdc) chip enable nsmre o smart media card (ssfdc) read enable nsmrb i smart media card (ssfdc) ready/nbusy signal. this is open-drain output so it requires a pull- up resistor. refer to figure 2-1. 208 pin diagram. 9.8.2 registers address name width default description 0x8005.c000 smccmd 32 0x0 smartmedia card command register 0x8005.c004 smcadr 27 0x0 smartmedia card address register 0x8005.c008 smcdatw 32 0x0 data written to smartmedia card 0x8005.c00c smcdatr 32 0x0 data received from smartmedia card 0x8005.c010 smcconf 8 0x0 smartmedia card controller configuration register 0x8005.c014 smctime 20 0x0 timing parameter register 0x8005.c01c smcstat 32 0x0 smartmedia card controller status register 0x8005.c024 smcecc1 24 0x0 ecc register for first half page data 0x8005.c028 smcecc2 24 0x0 ecc register for second half page data 0x8005.c02c smcmrw 12 0x0 multi-page read/write configuration register 0x8005.c030 smcmstat 12 0x0 multi-page read/write status register 0x8005.c034 smcebicon 3 0x0 smc control register using ebi interface table 9-12 smartmedia controller register summary
amba peripherals (smc controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 197 - 9.8.2.1 smc command regist er (smccmd) 0x8005.c000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 hidden command 0 hidden command 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 main command second command bits type function 31:24 r/w hidden command 0. this unique id feature will be available to 128mb nand flash and upward density products to prevent illegal copy of music files. unique id is put into redundant block of smartmedia. use this hidden command to access redundant block that cannot be accessed with open command, this byte filed is ignored when user block is accessed. for more information, refer to smartmedia maker?s datasheet. 23:16 r/w hidden command 1. read id command returns whether the smartmedia card supports unique id or not. hidden 2 step command for samsung is 30h-65h and for toshiba is 5ah-b5h. to return back to user block after accessing redundant block area, reset command (ffh) should be carried out. 15:8 r/w there are 9 commands to operate smartmedia card. this controller supports only parts of them (bold type). set 1 st command into this byte field except writing to smartmedia. for write operation, set this byte field to serial data input (80h) and set second command byte field to page program (10h). function 1 st cycle 2 nd cycle function 1 st cycle 2 nd cycle serial data input 80h page program 10h read 0 00h block erase 60h d0h read 1 01h status read 70h read 2 50h id read 90h reset ffh 7:0 r/w set 2 nd command here
amba peripherals (smc controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 198 - 9.8.2.2 smc address register (smcadr) 0x8005.c004 26 25 24 23 22 21 20 19 18 17 16 smcadr26 ~ smcadr16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 smcadr15 ~ smcadr0 bits type function 26:0 r/w smc address. smc controller begins to operate after writing an address to smcadr. hence a valid command must be set to smccmd before writing to smcadr. however, reset and status read commands activate smc controller after writing to smccmd because they do not require an address. following table shows valid address range according to smartmedia card size. model valid page address 4 mb smcadr0 ~ smcadr21 8 mb smcadr0 ~ smcadr22 16 mb smcadr0 ~ smcadr23 32 mb smcadr0 ~ smcadr24 64 mb smcadr0 ~ smcadr25 128 mb smcadr0 ~ smcadr26
amba peripherals (smc controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 199 - 9.8.2.3 smc data write register (smcdatw) 0x8005.c008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n * (smcadr + 3)?s byte data n * (smcadr + 2)?s byte data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 n * (smcadr + 1)?s byte data n * smcadr?s byte data bits type function 31:0 r/w four byte data written to this register will be sent to smartmedia. smc controller receives a 32bit data from host controller. then it starts to transmit from least significant byte to most significant byte, one byte at a time. this smc controller writes a whole page at a single write transaction, so it requires 132 times consecutive writing (528 = 512+16 bytes). a page program process is as follows: set smccmd to xxxx8010h (sequential data input + page program), smcadr to desired target page address space, and then write first 4 byte data onto smcdatw. in normal mode, interrupt will be generated every 4 bytes write. at the end of sequential data input, smartmedia goes into page program mode by transmitting the second command to smartmedia. usually page program takes long time, no polling status register is recommended. smc controller automatically generates write finish interrupt when smartmedia comes back to ready mode. 9.8.2.4 smc data read register (smcdatr) 0x8005.c00c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 n * (smcadr + 3)?s byte data n * (smcadr + 2)?s byte data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 n * (smcadr + 1)?s byte data n * smcadr?s byte data bits type function 31:0 r four byte data read from smartmedia is stored in this register. smc controller receives a byte data from smartmedia and stores it into 4 byte internal buffer to create 32bit data. first read byte data is stored at least significant byte and fourth byte data is stored at most significant byte of buffer. host controller reads this register to get 4 byte data at a time. this smc controller reads a whole page at a single read transaction, so it requires 132 times consecutive reading. a page reading process is as follows: set smccmd to xxxx00yyh (xxxx can be unique id if redundant area accessed, yy is don?t care. only 00h command is valid. no 01h or 50h command supported) and then set smcadr to target page address. smc controller will access smartmedia with given command and address. interrupt will be generated after first four byte read. like writing process, reading process reads a whole 528 byte in a page at a single transaction, so interrupt will be 132 times. against to write operation, there is no read finish interrupt because we can count the number of read transfers in software or can get the total access word size from byte count of smcstat.
amba peripherals (smc controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 200 - 9.8.2.5 smc configuration register (smcconf) 0x8005.c010 31 30 29 28 27 26 25 24 power enable - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - multi-page write enalbe multi-page read enalbe write ecc enable 7 6 5 4 3 2 1 0 read ecc enable safe margin smc enable - intr en - unique id en big card enable bits type function 31 r/w power on bit. to activate smc controller, set this bit. reset will fall the controller into the deep sleep mode. 30:11 - reserved. keep these bits to zero. 10 r/w multi-page write enable bit. when this bit set, data can be stored in smc continuously up to 32 pages. while the single page write requires write command and address for each operation, it does not necessary write command and address for each page. 9 r/w multi-page read enable bit. when this bit set, data stored in smc can be read continuously up to 32 pages. while the single page read requires read command and address for each operation, it does not necessary read command and address for each page. 8 r/w ecc write enable bit. when this bit set, 3 byte ecc code (specified in ssfdc standard) is generated in ecc block and written to smartmedia. 7 r/w ecc read & check enable bit. when this bit set, 3 byte ecc code is read out from smartmedia and compared with regenerated ecc code, for which the data read out from smartmedia is used. the result is returned to a host when a host reads ecc area in redundant area. 6 r/w safe margin enable bit. in normal mode, chip select signal changes simultaneously with read enable and write enable signals. but when this bit set, the duration of read and write enable signal applied to smartmedia is reduced by 1 automatically. by enabling this, the rising edge of read and write enable signal will be earlier than the rising edge of chip enable, which guarantees latching data safely. 5 r/w smc controller enable bit. reset this bit will make smc controller stay in standby mode. no interrupt generated, no action occurred. 4 - reserved. keep these bits to zero. 3 r/w interrupt enable. after reading a word or before writing a word, the interrupt bit of smcstat will be set and interrupt will occur if intr en is enabled. if this bit is disabled, software must poll the interrupt flag of smcstat to know the occurrence of an interrupt. after writing a whole page (or pages when cont page en is enabled) to smartmedia, write finish interrupt will also be generated to notice that the smartmedia complete the write operation successfully. 2 - reserved. keep these bits to zero. 1 r/w redundant page enable. when use smartmedia with unique id and want to access redundant page area, set high. this bit cannot be cleared automatically, so in order to read open page area clear this bit and set a reset command to smccmd. 0 r/w larger than 32mb smartmedia support enable. when using 64mb or 128mb smartmedia, set this bit high.
amba peripherals (smc controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 201 - 9.8.2.6 smc timing parameter register (smctime) 0x8005.c014 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 - wait counter - byte counter 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - high counter - - - - - low counter bits type function 31:28 - reserved. keep these bits to zero. 27:24 r/w wait counter maximum limit value. waiting time delay between address latch and write data in page program mode or between address latch and read data in read id mode and read status register is determined by this register. 0000 = 1 bclk width 0001 = 2 bclk width ? 1111 = 16 bclk width 23 - reserved 22:16 r/w should set these bits as 0x7f to access full 512 bytes page at one access command (read or program). 15:10 - reserved 9:8 r/w high pulse width value of read enable and write enable signal. the width must satisfy the ac characteristics of smartmedia to guarantee correct transfer of data. with safety margin enable, width will be decreased by one. 00 = 1 bclk width (0 bclk with safety margin enable. don?t make this case) 01 = 2 bclk width (1 bclk with safety margin enable) 10 = 3 bclk width (2 bclk with safety margin enable) 11 = 4 bclk width (3 bclk with safety margin enable) 7:3 - reserved 2:0 r/w low pulse width value of read enable and write enable signal. the width must satisfy the ac characteristics of smartmedia to guarantee correct transfer of data. with safety margin enable, width will be decreased by one. 000 = 1 bclk width (0 bclk with safety margin enable, don?t make this case) 001 = 2 bclk width (1 bclk with safety margin enable) ? 111 = 8 bclk width (7 bclk with safety margin enable)
amba peripherals (smc controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 202 - 9.8.2.7 smc status register (smcstat) 0x8005.c01c 31 30 29 28 27 26 25 24 cd intr nsmce smcle smale nsmwe nsmre nsmwp smr/b 23 22 21 20 19 18 17 16 current command/card detect notification 15 14 13 12 11 10 9 8 extra area byte count 7 6 5 4 3 2 1 0 internal state card detect irq - busy bits type function 31 r card detect interrupt. when card inserted or removed, card detect interrupt will be generated. in the interrupt service routine, look at this bit to identify interrupt type. 30:24 r current status of output signals. 23:16 r current active command. if in card detect interrupt, this byte shows 0xcd. 15 r set when extra area of a page is accessed. 14:8 r current address of a page in word units. 7:4 r shows internal state machine?s state. 3 r set when smc enable and smc card inserted. it will be zero when card removed. 2 r interrupt flag 1 - reserved 0 r reset shows smc is in idle mode. set means smc in working mode.
amba peripherals (smc controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 203 - 9.8.2.8 smc first half page ecc register (smcecc1) it contains generated ecc value of 0~255th byte in an page. especially, it is used to calculate the error position with ecc data stored in smc in reading operation. 0x8005.c024 23 22 21 20 19 18 17 16 p4 p4? p2 p2? p1 p1? 1 1 15 14 13 12 11 10 9 8 p1024 p1024? p512 p512? p256 p256? p128 p128? 7 6 5 4 3 2 1 0 p64 p64? p32 p32? p16 p16? p8 p8? bits type function 31:24 r reserved. 23,21,19 r bit position vector. it is used to calculate the bit position in the byte having error. 22,20,18 r complementary value of bit position vector. 17 r reserved. 16 r reserved. 15,13,11,9, 7,5,3,1 r byte position vector. it is used to calculated the byte position in the first half page having error. 14,12,10,8, 6,4,2,0 r complementary value of byte position vector.
amba peripherals (smc controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 204 - 9.8.2.9 smc second half page ecc register (smcecc2) it contains generated ecc value of 256~511 st byte in an page. especially, it is used to calculate the error position with ecc data stored in smc in reading operation. 0x8005.c028 23 22 21 20 19 18 17 16 p4 p4? p2 p2? p1 p1? 1 1 15 14 13 12 11 10 9 8 p1024 p1024? p512 p512? p256 p256? p128 p128? 7 6 5 4 3 2 1 0 p64 p64? p32 p32? p16 p16? p8 p8? bits type function 31:24 r reserved. 23,21,19 r bit position vector. it is used to calculate the bit position in the byte having error. 22,20,18 r complementary value of bit position vector. 17 r reserved. 16 r reserved. 15,13,11,9, 7,5,3,1 r byte position vector. it is used to calculated the byte position in the second half page having error. 14,12,10,8, 6,4,2,0 r complementary value of byte position vector.
amba peripherals (smc controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 205 - 9.8.2.10 smc multi-page read/write configuration register (smcmrw) 0x8005.c02c 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - page size for write page size for read bits type function 31:12 - reserved. keep these bits to zero. 11:6 r/w multi-page write size bit. maximum 32 pages can be written to smc with single command and start address. 000000 = no writing. 000001 = 1 pages. 000010 = 2 pages. ? 011111 = 31 pages. 100000 = 32 pages 5:0 r/w multi-page read size bit. maximum 32 pages can be read from smc with single command and start address. 000000 = no reading. 000001 = 1 pages. 000010 = 2 pages. ? 011111 = 31 pages. 100000 = 32 pages. 9.8.2.11 smc multi-page read/write status register (smcstat) 0x8005.c030 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - write page count read page count bits type function 31:12 - reserved. keep these bits to zero. 11:6 r/w current page count in multi-page writing operation. during a page write operation, it is equal to (current page count -1 ). after full one page (528byte) writing, it becomes ?current page count?. 5:0 r/w current page count in multi-page reading operation. during a page read operation, it is equal to (current page count -1 ). after full one page (528byte) reading, it becomes ?current page count?.
amba peripherals (smc controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 206 - 9.8.2.12 smc control register using ebi interface (smcebicon) 0x8005.c034 7 6 5 4 3 2 1 0 - - - - - smc access select nsmwp nsmce bits type function 31:3 - reserved 2 w smc access mode select. when this bit set (=1), ebi interface controls smc. when this bit unset (=0), smc controller controls smc. 1 w nsmwp control for smc control using ebi interface. when bit [2] is used to set nsmwp of smc. 0 w nsmce control for smc control using ebi interface. when bit [2] is used to set nsmce of smc.
amba peripherals (smc controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 207 - 9.8.3 smc access using ebi interface HMS30C7210 provides 2 methods to access smc memory. one is the smc controller and the other is the smi controller. smc access scheme of the smc controller in HMS30C7210 is different than that of the smi controller. if an user want to access the smc like as the sram, smi controller must be used with the regi ster ?smcebicon? (address 0x8005.c034). the figure below shows the scheme in the HMS30C7210 for the smc access using the ebi interface (ecc is not supported at this method). the following represents the smc access method using the ebi interface. ? the bit 2 of the register ?smcebicon? must be set to ?1?. ? the memory address, which enables the nrcs[3], must be used. ? when the 2 least significant bits of the memory address is equal to ?01? (ra[1:0]=?01?), the signal smcle is set. ? when the 2 least significant bits of the memory address is equal to ?10? (ra[1:0]=?01?), the signal smale is set. ? the bit 1 of the reigster ?smcebicon? set the signal nsmwp. ? the bit 0 of the reigster ?smcebicon? set the signal nsmce. HMS30C7210 mux mux mux mux mux mux smcebicon[2] smcle nsmwe smale nsmre nsmce nsmwp nsmrb ra[0] nrwe[0] ra[1] nroe smcebicon[0] smcebicon[1] gpio portc[1] nrcs[3] mux mux mux mux mux mux smcebicon[2] smcle nsmwe smale nsmre nsmce nsmwp nsmrb ra[0] nrwe[0] ra[1] nroe smcebicon[0] smcebicon[1] gpio portc[1] nrcs[3] figure 9-26. smc access using the ebi interface
amba peripherals (smc controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 208 -
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 209 - 9.9 timer & pwm this module is a 16-bit counter clocked by pclk. the frequency of pclk is approximately 3.6923mhz when f cclk is 48mhz and obtained by the formula f pclk = f cclk / 13, where f pclk is the frequency of pclk and f cclk is the frequency of cclk. timer/pwm is an amba slave module that connects to the advanced peripheral bus (apb). for more information about amba, pl ease refer to the amba specification (arm ihi 0001). the main features of timer module are : ? 8/16-bit up counter ? auto repeat mode ? count enable/disable ? interrupt enable/disable ? 4-timer channel and 4 timer outputs the main features of pwm modules are : ? 16-bit up counter ? count enable/disable ? 2-pwm channel and 2 pwm outputs ? adjustable pwm output period and duty ratio t0count [15:8] t0 base t0 comparator t0 output control timer0out t0count [7:0] apb i/f t0ctrl t3count [15:8] t3 base t3 comparator t3 output control timer3out t3count [7:0] t3ctrl ...... timer2out timer1out p0count p0 width p0 period p0 width comparator p0 period comparator p0ctrl p0 output control pwm0out p1count p1 width p1 period p1 width comparator p1 period comparator p1ctrl p1 output control pwm1out figure 9-27. block diagram of timer/pwm
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 210 - 9.9.1 external signals pin name* type description pwm [1:0] o the outputs of 2 pwm channels timer[3:0] o the outputs of 4 timer channels refer to figure 2-1. 208 pin diagram. 9.9.2 registers address name width default description 0x8005.d000 t0base 16 0xffff timer0 base register 0x8005.d008 t0count 16 0x0 timer0 counter register 0x8005 d00c t0stat 1 0x0 timer0 status register 0x8005.d010 t0ctrl 8 0x0 timer0 control register 0x8005.d020 t1base 16 0xffff timer1 base register 0x8005.d028 t1count 16 0x0 timer1 counter register 0x8005 d02c t1stat 1 0x0 timer1 status register 0x8005.d030 t1ctrl 8 0x00 timer1 control register 0x8005.d040 t2base 16 0xffff timer2 base register 0x8005.d048 t2count 16 0x0 timer2 counter register 0x8005 d04c t2stat 1 0x0 timer2 status register 0x8005.d050 t2ctrl 8 0x0 timer2 control register 0x8005.d060 t3base 16 0xffff timer3 base register 0x8005 d068 t3count 16 0x0 timer3 counter register 0x8005 d06c t3stat 1 0x0 timer3 status register 0x8005 d070 t3ctrl 8 0x0 timer3 control register 0x8005 d080 topctrl 10 0x0 top-level control register 0x8005.d084 topstat 4 0x0 top-level status register 0x8005.d0a0 p0count 16 0x0 pwm channel 0 count register 0x8005.d0a4 p0width 16 0xffff pwm channel 0 width register 0x8005.d0a8 p0period 16 0xffff pwm channel 0 period register 0x8005.d0ac p0ctrl 8 0x0 pwm channel 0 control register 0x8005.d0c0 p1count 16 0x0 pwm channel 1 count register 0x8005.d0c4 p1width 16 0xffff pwm channel 1 width register 0x8005.d0c8 p1period 16 0xffff pwm channel 1 period register 0x8005.d0cc p1ctrl 8 0x0 pwm channel 1 control register table 9-13. timer register summary
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 211 - 9.9.2.1 timer top-level control register (topctrl) 0x8005.d080 15 14 13 12 11 10 9 8 - - - - - - timer3 outen timer2 outen 7 6 5 4 3 2 1 0 timer1 outen timer0 outen timer3 clksel npower down timer3 inten timer2 inten timer1 inten timer0 inten bits type function 9 r/w timer channel 3 output enable setting this bit enables the output of timer channel 3 to propagate through pin timer[3]. whenever t3count reaches t3base, the output of timer channel 3(timer[3]) toggles. if a system reset or softreset in t3ctrl register occurs, the output is reset to ?0?. 0 = output of timer channel 3 is blocked. (default) 1 = output of timer channel 3 appears on pin timer[3]. 8 r/w timer channel 2 output enable setting this bit enables the output of timer channel 2 to propagate through pin timer[2]. whenever t2count reaches t2base, the output of timer channel 2(timer[2]) toggles. if a system reset or softreset in t2ctrl register occurs, the output is reset to ?0?. 0 = output of timer channel 2 is blocked. (default) 1 = output of timer channel 2 appears on pin timer[2]. 7 r/w timer channel 1 output enable setting this bit enables the output of timer channel 1 to propagate through pin timer[1]. whenever t1count reaches t1base, the output of timer channel 1(timer[1]) toggles. if a system reset or softreset in t1ctrl register occurs, the output is reset to ?0?. 0 = output of timer channel 1 is blocked. (default) 1 = output of timer channel 1 appears on pin timer[1]. 6 r/w timer channel 0 output enable setting this bit enables the output of timer channel 0 to propagate through pin timer[0]. whenever t0count reaches t0base, the output of timer channel 0(timer[0]) toggles. if a system reset or softreset in t0ctrl register occurs, the output is reset to ?0?. 0 = output of timer channel 0 is blocked. (default) 1 = output of timer channel 0 appears on pin timer[0]. 5 r/w timer channel 3 clock source all counters in timer channel 0,1,2,3 operate in pclk domain. but timer channel 3 select the clock source of 16bit timer 3. (for details, see operation section) 0 = t3count is clocked by pclk. (default) 1 = t3count is clocked when t2count reaches t2base. 4 r/w power down mode (active low) activates timer/pwm module by supplying pclk. 0 = indicates power down mode and clock signal(pclk) is always ?0?. (default) 1 = supply pclk to timer/pwm module (normal operation mode). 3 r/w timer channel 3 interrupt enable setting this bit enables generation of interrupt signal from timer channel 3. 0 = no interrupt is requested from timer channel 3. (default) 1 = interrupt is generated when t3count reaches t3base. 2 r/w timer channel 2 interrupt enable setting this bit enables generation of interrupt signal from timer channel 2. 0 = no interrupt is requested from timer channel 2. (default) 1 = interrupt is generated when t2count reaches t2base. 1 r/w timer channel 1 interrupt enable setting this bit enables generation of interrupt signal from timer channel 1. 0 = no interrupt is requested from timer channel 1. (default) 1 = interrupt is generated when t1count reaches t1base. 0 r/w timer channel 0 interrupt enable setting this bit enables generation of interrupt signal from timer channel 0.
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 212 - 0 = no interrupt is requested from timer channel 0. (default) 1 = interrupt is generated when t0count reaches t0base. 9.9.2.2 timer status register (topstat) 0x8005.d084 7 6 5 4 3 2 1 0 - - - - timer3 match timer2 match timer1 match timer0 match bits type function 7:4 - reserved 3 r this bit reflect the status of st bit in t3stat 0 = match bit in t3stat is cleared. 1 = match bit in t3stat is set. 2 r this bit reflect the status of st bit in t2stat 0 = match bit in t2stat is cleared. 1 = match bit in t2stat is set. 1 r this bit reflect the status of st bit in t1stat 0 = match bit in t1stat is cleared. 1 = match bit in t1stat is set. 0 r this bit reflect the status of st bit in t0stat 0 = match bit in t0stat is cleared. 1 = match bit in t0stat is set.
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 213 - 9.9.2.3 timer [0,1,2,3] base register (t[0,1,2,3]base) 0x8005.d000 / 0x8005.d020 / 0x8005.d040 / 0x8005 d060 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t[0,1,2,3]base [15:0] bits type function 15:0 r/w timer 0 (timer 1, timer 2, timer3) base register this register is used to limit the upper boundary of tncount(n = 0,1,2,3). when tncount reaches tnbase, the tncount is cleared and each timer channel may generate an interrupt. and also the output of each timer channel may toggle. the initial value of tnbase is 0xffff. 9.9.2.4 timer [0,1,2,3] count register (t[0,1,2,3]count) 0x8005.d008 / 0x8005.d028 / 0x8005.d048 / 0x8005 d068 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t[0,1,2,3]count [15:0] bits type function 15:0 r/w timer 0 (timer1, timer2, timer3) up counter the clock source of this count is controlled by prescaler in tnctrl(n = 0,1,2,3). tncount is not loadable. the initial value of tncount is 0x0000.
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 214 - 9.9.2.5 timer [0,1,2,3] control register (t[0,1,2,3]ctrl) 0x8005.d010 / 0x8005.d030 / 0x8005.d050 / 0x8005 d070 7 6 5 4 3 2 1 0 prescaler byte mode soft reset repeat mode count enable bits type function counter clock prescaler tncount is clocked by (prescaler + 1)th clk(n = 0,1,2,3). the symbol clk represents normally pclk or the moment when t2count equals t2base. prescaler clock source 7:4 r/w 0000 0001 0010 0011 ? 1110 1111 clk (default) clk/2 clk/3 clk/4 ? clk/15 clk/16 3 r/w byte mode. if bytemode is set, each tncount operates as 8-bit counter and the upper limit of tncount is 0xff. 0 = tncount operates as normal 16-bit counter. (default) 1 = tncount operates as 8-bit counter and is cleared when it reaches 0xff. 2 r/w software reset command this bit resets tncount and the output of each timer channel. this bit is not auto-cleared so user should clear this bit after issuing softreset command. 0 = normal operation. (default) 1 = resets tncount and output of timer channel. 1 r/w when this bit is set, tncount repeats the following actions until repeatmode is cleared : tncount increments ? reaches tnbase ? clears ? increments ? ? 0 = tncount stops counting when tncount reaches tnbase. (default) 1 = tncount increments repeatedly while countenable in tnctrl is set. 0 r/w counter enable setting this bit enables tncount to increment and this bit will be cleared automatically when tncount reaches tnbase if repeatmode is ?0?. 0 = stops counting. (default) 1 = starts counting. 9.9.2.6 timer [0,1,2,3] status register (t[0,1,2,3]stat) 0x8005.d00c / 0x8005.d02c / 0x8005.d04c / 0x8005 d06c 7 6 5 4 3 2 1 0 - - - - - - - match bits type function 7:1 - reserved 0 r tncount match match bit is set when tncount equals tnbase. writing any value to tnstat clears match bit and disables interrupt request when interrupt is pending. 0 = tnstat is cleared or tncount not equals tnbase. (default) 1 = tncount reached tnbase.
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 215 - 9.9.2.7 pwm channel [0,1] count register (p[0,1]count) 0x8005.d0a0 / 0x8005.d0c0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p[0,1]count bits type function 15:0 r pwm 0 (pwm 1) up counter the clock source of this count is controlled by prescaler in pnctrl(n = 0,1). pncount is not loadable. the initial value of pncount is 0x0000. 9.9.2.8 pwm channel [0,1] width register (p[0,1]width) 0x8005.d0a4 / 0x8005.d0c4 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p[0,1]width bits type function 15:0 r/w pwm 0 (pwm 1) width register when outputinvert in pnctrl is ?0?, the value written in this register represents the duration of pwm output?s high level. when outputinvert in pnctrl is ?1?, the value written in this register represents the duration of pwm output?s low level. 9.9.2.9 pwm channel [0,1] period register (p[0,1]period) 0x8005.d0a8 / 0x8005.d0c8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p[0,1]period bits type function 15:0 r/w pwm 0 (pwm 1) period register this register is used to define 1 period of pwm output. when pncount reaches pnperiod, the counter resets to 0x0000 and starts counting again.
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 216 - 9.9.2.10 pwm channel [0,1] control register (p[0,1]ctrl) 0x8005.d0ac / 0x8005.d0cc 7 6 5 4 3 2 1 0 prescaler output invert output enable soft reset pwm enable bits type function counter clock prescaler pncount is clocked by (prescaler + 1)th pclk(n = 0,1). prescaler clock source 7:4 r/w 0000 0001 0010 0011 ? 1110 1111 pclk (default) pclk/2 pclk/3 pclk/4 ? pclk/15 pclk/16 3 r/w pwm output waveform inverting normally the pwm output is low when pncount reaches pnwidth and high when pncount reaches pnperiod. setting this bit makes the polarity of pwm output to be inverted. if this bit is set, the pwm output is high when pncount reaches pnwidth and low when pncount reaches pnperiod. the initial value of pwm output is high regardless of outputinvert in pnctrl. 0 = pwm output is not inverted. (default) 1 = pwm output is inverted. 2 r/w pwm output enable setting this bit enables the output of each pwm channel to propagate through pin pwm[0] or pwm[1]. if a system reset or softreset in pnctrl register occurs, the output is reset to ?0?. 0 = output propagation is disabled. (default) 1 = output propagation is enabled. 1 r/w software reset command this bit resets pncount and the output of each pwm channel. this bit is not auto-cleared so user should clear this bit after issuing softreset command. 0 = normal operation. (default) 1 = resets pncount and output of pwm channel. 0 r/w counter enable. setting this bit enables pncount to increment. 0 = stops counting. (default) 1 = starts counting.
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 217 - 9.9.3 operation 9.9.3.1 timer counter clock sources the counter of each timer channel is clocked by the peripheral clock pclk. the clock source is selected by the clock select logic which is controlled by the prescaler bits in tnctrl. the counter can be clocked directly by the pclk by setting the prescaler ?0000?. this provides the fastest operation, with a maximum clock frequency equal to the pclk frequency(f pclk ). alternatively, one of 15 taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f pclk /2, f pclk /3, f pclk /4, ?, f pclk /14, or f pclk /16. the prescaler operates when prescaler in tnctrl is non-zero value, and each counter logic has it?s own clock select logic. the counter starts to counting upward after countenable in tnctrl is set. tncount [15:8] tn ctrl tncount [7:0] 16-bit counter softreset repeatmode countenable bytemode tn prescaler prescaler counter clock apb data bus npowerdown pclk top ctrl figure 9-28. clock select logic
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 218 - 9.9.3.2 repeat and non-repeat mode of timer channel there are two operation modes in each counter module which are non-repeat mode and repeat mode. in non-repeat mode, the counter stops when tncount reaches tnbase and an interrupt can be triggered if timerninten bit is set. also, the output of timer channel is toggled. in repeat mode, the counter is free-running until countenable is cleared. whenever tncount reaches tnbase, timer channel?s output toggles and an interrupt can be triggered. at the moment tncount equals to tnbase, the counter is cleared and starts counting from initial value(0x0000) while countenable is high. to operate timer in non-repeat mode, follow the steps below :
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 219 - non-repeat mode ? activate clock source by setting npowerdown ?1? and determine whether to propagate the output of timer channel or not. also determine whether interrupt is enabled or not. (topctrl) ? set the target value. (tnbase) ? select clock frequency and non-repeat mode. (tnctrl) ? start counting. (tnctrl) through out this chapter, the following symbols are used. pclk : peripheral clock pclk (cclk/13) countclk : clock source of counter which is pclk or it?s prescaled clock. timernout : output of each timer channel that can be propagated through timer[n]. timerninterrupt : interrupt source of each timer channel the following figure is an example of non-repeat mode operation. in this figure, see that countclk is stopped when tncount equals to tnbase and the lsb of tnctrl is cleared. these are the characteristics of non-repeat mode operation of timer. the output of timer channel changes and interrupt can be triggered when tncount equals to tnbase. pclk countclk tncount tnctrl tnbase timernout timerninterrupt 045b 045c 0x0460 045d 045e 045f 0460 0000 0x31 0x30 timerninten = 1 timerninten = 0 figure 9-29. non-repeat mode operation
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 220 - to operate timer in repeat mode, follow the steps below : repeat mode ? activate clock source by setting npowerdown ?1? and determine whether to propagate the output of timer channel or not. also determine whether interrupt is enabled or not. (topctrl) ? set the target value. (tnbase) ? select clock frequency and repeat mode. (tnctrl) ? start counting. (tnctrl) the following figure is an example of repeat mode operation. pclk countclk tncount tnctrl tnbase timernout timerninterrupt 00fe 00ff 0x0100 0100 0000 00fe 00ff 0x33 0x33 interrupt may be generated 0100 0000 figure 9-30. repeat mode operation as it can be seen in the above figure, countclk is not stopped while countenable is high. and timernout changes it?s value at the moment tncount equals to tnbase.
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 221 - 9.9.3.3 8-bit timer operation normally tncount is 16-bit up counter. and if tnbase is at it?s reset value, tncount increments up to 0xffff and then overflows(overflow interrupt is not supported). but tncount can also used as 8-bit counter by setting bytemode to operate timer in repeatmode, follow the steps below : byte mode ? activate clock source by setting npowerdown ?1? and determine whether to propagate the output of timer channel or not. also determine whether interrupt is enabled or not. (topctrl) ? set the target value. (tnbase) ? select clock frequency and determiner repeat or non-repeat mode. (tnctrl) ? select byte mode and start counting. (tnctrl) the following figure is an example of byte counter in non-repeat mode operation. note that the timing and operation is the same as normal 16-bit counter in non-repeat mode when tnbase is less than or equal to ?0xff?. pclk countclk tncount tnctrl tnbase timernout timerninterrupt 0020 0021 0x0050 004e 004f 0050 0000 0x39 0x38 0x39 timerninten = 1 timerninten = 0 figure 9-31. byte counter operation in non-repeat mode
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 222 - the following figure is an example of byte counter in repeat mode operation. note that tnbase is out of the range of 8-bit counter, so tncount never reaches tnbase therefore no interrupt is triggered and output of timer maintain previous value. except that it is the same as normal 16-bit counter in repeat mode operation. pclk countclk tncount tnctrl tnbase timernout timerninterrupt 0020 0021 0x0460 00fd 00fe 00ff 0000 0x3b 0x3b 0001 0002 figure 9-32. byte counter operation in repeat mode
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 223 - 9.9.3.4 timer channel 3 clock source change counters of all timer channel are clocked by pclk or it?s prescaled clock. but counter of timer channel 3 has additional clock source. when timer3cl ksel in topctrl is set, t3count is clocked w hen t2count equals to t2base(t2match event). even if t3count is clocked by t2match event, the prescaler of timer channel 3 works. in the following figure, the prescaler value of timer channel 3 is ?0?, so at each t2match event t3count is clocked. pclk count2clk t2count t2ctrl t2base timer2out count3clk t3count t3ctrl topctrl 00fe 00ff 0x0100 0100 0000 00fe 00ff 0x33 0x33 0100 0000 0003 0x03 0x03 0005 0004 0004 0x330 0x330 figure 9-33. clock source of t3count is t2match event
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 224 - 9.9.3.5 timer soft reset when softreset in tnctrl is set, counter and output of timer channel n is cleared. note that softreset bit is not auto-cleared, so tnctrl must be re-written to start counting again. softreset is an asynchronous reset input to counter module, so while softreset is high, the counter and output are in their reset state. pclk countclk tncount tnctrl tnbase timernout timerninterrupt 045e 045f 0x0460 0460 0000 0001 0000 0001 0x33 0x33 timerninten = 1 timerninten = 0 0x37 figure 9-34. software issued reset command
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 225 - 9.9.3.6 timer output and interrupt generation there is only one interrupt condition in each timer channel and it?s match event of tncount. as seen below, tncount increments after countenable is set. when tncount reaches tnbase (match condition), the counter is cleared and timer output is toggled, and if interrupt generation is enabled by timerninten timer interrupt is also requested. if timer operates in repeat mode, the counter continues to increment from 0x0000. if match condition occurs, the match bit in tnstat is set. the following figure is an example of counter in repeat mode operation. countenable = 1 output of timer channel n toggles time 0xffff tnbase 0x0000 tncount timerout interrupt interrupt cleared by software figure 9-35. output and interrupt generation in repeat mode
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 226 - the following figure is an example of counter in non-repeat mode operation. all is the same as above but when match condition occurs the counter stops. countenable = 1 output of timer channel n toggles & tncount is stopped time 0xffff tnbase 0x0000 tncount timerout interrupt interrupt cleared by software figure 9-36. output and interrupt generation in non-repeat mode
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 227 - 9.9.3.7 pwm counter clock sources the counter of each pwm channel is clocked by the peripheral clock pclk. the clock source is selected by the clock select logic which is controlled by the prescaler bits in pnctrl. the pwm counter can be clocked directly by the pclk by setting the prescaler ?0000?. this provides the fastest operation, with a maximum clock frequency equal to the pclk frequency(f pclk ). alternatively, one of 15 taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f pclk /2, f pclk /3, f pclk /4, ?, f pclk /14, or f pclk /16. the prescaler operates when prescaler in pnctrl is non-zero value, and each counter logic has it?s own clock select logic. the counter starts to counting upward after pwmenable in pnctrl is set. pn ctrl pncount[15:0] 16-bit up counter softreset pwmenable counter clock apb data bus pn prescaler prescaler npowerdown pclk top ctrl clk figure 9-37. clock select logic ? activate clock source by setting npowerdown ?1?. (topctrl) ? set the pwm period and duration. (pnperiod, pnwidth) ? determine whether to propagate the output of pwm channel or not. (pnctrl) ? select clock frequency and start counting. (pnctrl)
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 228 - 9.9.3.8 pwm output generation pwm output?s duty and period is controlled by the registers pnwidth and pnperiod. when outputinvert is ?0? : pwm output goes low when pncount reaches pnwidth and continues to increment. when pncount reaches pnperiod, pwm output goes high and pncount is cleared. this is repeated until pwmenable is high. in this setting pnwidth is the duration of high level of pwm output. the following figure shows the example of pwm waveform when outputinvert is ?0?. at reset, pwmout is high. pclk countclk pncount pnctrl pnwidth pnperiod widthmatch periodmatch pwmnout 001e 001f 0x0020 00fe 00ff 0100 0x35 0x35 0000 0001 0020 0x0100 figure 9-38. timing diagram of pwm channel when outputinvert = 0
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 229 - when outputinvert is ?1? : pwm output goes high when pncount reaches pnwidth and continues to increment. when pncount reaches pnperiod, pwm output goes low and pncount is cleared. this is repeated until pwmenable is high. in this setting pnwidth is the duration of low level of pwm output. the following figure shows the example of pwm waveform when outputinvert is ?1?. pclk countclk pncount pnctrl pnwidth pnperiod widthmatch periodmatch pwmnout 001e 001f 0x0020 00fe 00ff 0100 0x3d 0x3d 0000 0001 0020 0x0100 figure 9-39. timing diagram of pwm channel when outputinvert = 1
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 230 - 9.9.3.9 pwm duty control when outputinvert is ?0? : in this setting pnwidth is the duration of high level of pwm output. below 2 figures show the waveform of pwm output for 30% and 80% duty ratio when outputinvert is ?0?. pncount 0xffff (=pnperiod) 0x7fff pnwidth 0x0000 pwmout time figure 9-40. pwm waveform when outputinvet = 0, duty = 30% pncount 0xffff (=pnperiod) pnwidth 0x7fff 0x0000 pwmout time figure 9-41. pwm waveform when outputinvet = 0, duty = 80% the frequency of pwm output is calculated by the equation f pw m = f countclk / pnperiod where f countclk is the frequency of clock source of pwm counter. hence the value of pnperiod affects the period of pwm output. if the value pnperiod is fixed, changing the value of pnwidth extends or shrinks the length of high level of pwm output with period fixed. hence the value of
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 231 - pnwidth affects the duty ratio of pwm output. if pnwidth is greater than pnperiod, the pwm output is always high. 50% duty ratio is achieved by setting pnwidth half of pnperiod. at reset, pwmout is high.
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 232 - when outputinvert is ?1? : in this setting pnwidth is the duration of low level of pwm output. below 2 figures show the waveform of pwm output for 30% and 80% duty ratio when outputinvert is ?1?. pncount 0xffff (=pnperiod) 0x7fff pnwidth 0x0000 pwmout time figure 9-42. pwm waveform when outputinvet = 1, duty = 30% pncount 0xffff (=pnperiod) pnwidth 0x7fff 0x0000 pwmout time figure 9-43. pwm waveform when outputinvet = 1, duty = 80% note that the initial value of pwmout is high, so the 1 st period of pwm output is always high when outputinvert is ?1?.
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 233 - 9.9.3.10 timer soft reset like timer module, when softreset in pnctrl is set, counter and output of pwm channel n is cleared. note that softreset bit is not auto-cleared, so pnctrl must be re-written to start counting again. softreset is an asynchronous reset input to counter module, so while softreset is high, the counter and output are in their reset state. pclk countclk pncount pnctrl pnwidth pnperiod pwmnout 045e 045f 0x0300 0460 0000 0001 0000 0001 0x35 0x35 0x37 0x0460 figure 9-44. software issued reset command
amba peripherals (timer & pwm) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 234 -
amba peripherals (watchdog timer) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 235 - 9.10 watchdog timer the watchdog timer (wdt) has an one-channel for monitoring system operation. if a system becomes uncontrolled and the timer counter overflows without being rewritten correctly by the cpu, a reset signal is output to pmu. when this watchdog function is not needed, the wdt can be used as an interval timer. in the interval timer operation, an interval timer interrupt is generated at each counter overflow. features ? watchdog timer mode and interval timer mode ? interrupt signal intwdt to interrupt controller in the watchdog timer mode & interval timer mode ? output signal mnreset to pmu (power management unit) ? eight counter clock sources ? selection whether to reset the chip internally or not ? reset signal type: manual reset ? clock source is 32.768khz apb i/f clock divider 8-bit counter wdtclk comparator overflow mnrst control interrupt control intwdt mnrst 32.768khz figure 9-4 wdt block diagram
amba peripherals (watchdog timer) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 236 - 9.10.1 registers address name width default description 0x8005.e000 wdtctrl 8 0x0 timer/reset control 0x8005.e004 wdtstat 2 0x0 reset status 0x8005.e008 wdtcnt 8 0x0 timer counter table 9-14. watchdog timer register summary 9.10.1.1 wdt control register (wdtctrl) 0x8005.e000 7 6 5 4 3 2 1 0 inten modesel tmen mnrsten [4:3] clksel [2:0] bits type function 7 r/w the interrupt request enable when the value of wdtcnt register matches to 256 decimal value, an interrupt signal is generated. 0 = disable 1 = enable 6 r/w timer mode select select whether to use the wdt as a watchdog timer or interval timer. 0 = interval timer mode 1 = watchdog timer mode 5 r/w enable the wdt timer when this bit is set to ?0?, user can load data in wdtcnt register. 0 = disable 1 = enable 4:3 r/w mnrst output enable select whether to reset the chip internally or not if the tcnt overflows in the watchdog timer mode. 00 = disable 11 = mnrst output enable 2:0 r/w clock select the wdt has a clock generator which products eight counter clock sources. the clock signals are obtained by dividing the clock source. the clock source is 32.768khz. clksel[2:0] divide value divided clock max. overflow interval 000 2 16384 hz 15.6 ms 001 8 4096 hz 62.5 ms 010 32 1024 hz 0.25 s 64 512 hz 0.5 s 256 128 hz 2 s 512 64 hz 4 s 2048 16 hz 16 s 011 100 101 110 111 8192 4 hz 64 s
amba peripherals (watchdog timer) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 237 - 9.10.1.2 wdt status register (wdtstat) 0x8005.e004 7 6 5 4 3 2 1 0 - - - - - - itovf wtovf bits type function 7:2 - reserved 1 r interval timer interrupt flag this bit will be set to ?1? when wdtcnt has overflowed in the interval timer mode. this bit is reset to ?0? whenever the cpu reads the contents of this register. 0: interrupt was not generated or was cleared. 1: interrupt was generated. 0 r watchdog timer interrupt flag this bit will be set to ?1? when wdtcnt has overflowed in the watchdog timer mode. this bit is reset to ?0? whenever the cpu reads the contents of this register. 0: interrupt was not generated or was cleared. 1: interrupt was generated. 9.10.1.3 wdt counter (wdtcnt) 0x8005.e008 7 6 5 4 3 2 1 0 wdtcnt bits type function 7:0 r 8-bit up counter. when the timer is enabled, the timer counter starts counting pulse of the selected clock source. when the value of the wdtcnt changes from 0xff-0x00(overflows), a watchdog timer overflow signal is generated in the both timer modes. the wdtcnt is initialized to 0x00 by a power-reset.
amba peripherals (watchdog timer) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 238 - 9.10.2 watchdog timer operation 9.10.2.1 the watchdog timer mode to use the wdt as a watchdog timer, set the modesel and tmen bits of the wdtctrl register to ?1?. software must prevent wdtcnt overflow by rewriting the wdtcnt value (normally by writing 0x00) before overflow occurs. if the wdtcnt fails to be rewritten and overflow due to a system crash or the like, intwdt signal and mnrst signal are output. the intwdt signal is not output if the inten bit of wdtctrl register is disabled (inten = 0). the mnrsten bits of wdtctrl register should be set to ?11? for mnrst output. wdtcnt time ox00 oxff 0x00 written in wdtcnt wtovf = 1 fault and internal reset tmen = 1 modesel = 1 figure 9-5 wdt operation in the watchdog timer mode
amba peripherals (watchdog timer) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 239 - 9.10.2.2 the interval timer mode to use the wdt as an interval timer, clear modesel in wdtctrl register to ?0? and set tmen to ?1?. a interval timer interrupt (intwdt) is generated each time the timer counter overflows. this function can be used to generate interval timer interrupts at regular intervals. the mnrsten bits of wdtctrl register should be set to ?00? . wdtcnt value time ox00 oxff itovf = 1 int_wdt is generated tmen = 1 modesel = 0 figure 9-6 wdt operation in the interval timer mode 9.10.2.3 timing of setting the overflow flag in the interval timer mode when the wdtcnt overflows, the itovf flag is set to 1 and an watchdog timer interrupt (intwdt) is requested. in the watchdog timer mode when the wdtcnt overflows, the wtovf bit of the wdtstat is set to 1 and a wdtout signal is output. when rsten bit is set to 1, wdtcnt overflow enables an internal reset signal to be generated for the entire chip. 9.10.2.4 timing of clearing the overflow flag when the wdt status register (wdtstat) is read, the overflow flag is cleared.
amba peripherals (watchdog timer) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 240 - 9.10.2.5 examples of register setting interval timer mode (wdtcnt = 0x00 wdtctrl = 0xa0) wdtclk wdtcnt overflow rdstat itovf wtovf intwdt mnrst 0xfd 0xfe 0x10 0x11 0x01 0x02 0x00 0xff 0x00 0x01 0x12 0x13 figure 9-7 interrupt clear in the interval timer mode watchdog timer mode with internal reset disable (wdtcnt = 0x00 (normally) wdtctrl = 0xe0) wdtclk wdtcnt overflow rdstat itovf wtovf intwdt mnrst 0xfd 0xfe 0x10 0x11 0x01 0x02 0x00 0xff 0x00 0x01 0x12 0x13 figure 9-8 interrupt clear in the watchdog timer mode with mnrst disable
amba peripherals (watchdog timer) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 241 - watchdog timer mode with manual reset (wdtcnt = 0x00 wdtctrl = 0xf8) wdtclk wdtcnt overflow rdstat itovf wtovf intwdt mnrst bnres 0xfd 0xfe 0x10 0x00 0x01 0x02 0x00 0xff 0x00 0x01 figure 9-9 system reset generate in the watchdog timer mode with msrst enable
amba peripherals (watchdog timer) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 242 - 9.10.2.6 wdt setup flow watchdog timer flow ? set low to the tmen bit in wdtctrl register ? load the wished data in wdtcnt reigster (default is 8?b00) ? select the clksel, inten bits in wdtctrl register ? set high to the modesel bit in wdtctrl register ? set ?11? to the mnrsten bits in wdtctrl register ? set high to the tmen bit in wdtctrl register interval timer flow ? set low to the tmen bit in wdtctrl register ? load the wished data in wdtcnt reigster (default is 8?b00) ? select the clksel, inten bits in wdtctrl register ? set low to the modesel bit in wdtctrl register ? set ?00? to the mnrsten bits in wdtctrl register ? set high to the tmen bit in wdtctrl register
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 243 - 9.11 rtc the rtc works with an external 32768hz crystal oscillator. it comprises second- counter to year-counter clock and calendar circuits that feature automatic leap-year adjustment up to year 2099, alarm and tick-timer interrupt functions. also it can be operated by the backup battery while the system power down. the rtc has two event outputs, one which is synchronized to pclk, rtcirq, and the second, pwkup synchronized to the 32768hz clock. rtcirq is connected to the system interrupt controller, and pwkup is used by the pmu to provide a system alarm wake up. features ? rtc count second, minute, hour, day, day of week, month and year with leap- year compensation valid up to 2099 ? alarm interrupt or wake-up signal from power-down mode ? tick timer interrupt ? independent power pin ? write protection function figure 9-45. rtc block diagram
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 244 - as shown in figure 9-16, rtc module is connected to the apb. apb signals are refer to amba apb spec, and following table shows the non-amba signals from the rtc core block. the following table shows non-amba signals within rtc core block for more information about apb signals refer to the amba apb spec. name source/destination description clk32khz clock generator 32768hz clock input. this is the signal that clo cks the c ounter during normal operation. rtcirq apb(interrupt controller) asb(pmu) when high, this signal indicates a valid comparison between the counter value and the alarm register. it also indicates 1hz interval with enable bit in control register. this signal is used to interrupt controller. also it is used to wake up the HMS30C7210 when it is in deep sleep mode. tickirq apb(interrupt controller) tick timer interrupt signal. it is generated when tcnt value meets tbase value. table 9-15 non-amba signals within rtc core block 9.11.1 external signals pin name type description rtcoscin i rtc oscillator input. 32.768khz rtcoscout o rtc oscillator output. 32.768khz refer to figure 2-1. 208 pin diagram.
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 245 - 9.11.2 registers address name width default description write protect 0x8005.f000 rtctrl 6 0x1 rtc control register y 0x8005.f004 rtcstat 3 0x0 rtc status register - 0x8005.f008 rtcsec 7 0x0 rtc second register y 0x8005.f00c rtcmin 7 0x0 rtc minute register y 0x8005.f010 rtchor 6 0x0 rtc hour register y 0x8005.f014 rtcday 6 0x1 rtc day register y 0x8005.f018 rtcmon 5 0x1 rtc month register y 0x8005.f01c rtcyer 8 0x0 rtc year register y 0x8005.f020 rtcwek 3 0x0 rtc week register y 0x8005.f024 alctrl 8 0x0 alarm control register y 0x8005.f028 alsec 7 0x0 alarm second register y 0x8005.f02c almin 7 0x0 alarm minute register y 0x8005.f030 alhor 6 0x0 alarm hour register y 0x8005.f034 alday 6 0x1 alarm day register y 0x8005.f038 almon 5 0x1 alarm month register y 0x8005.f03c alyer 8 0x0 alarm year register y 0x8005.f040 alwek 3 0x0 alarm week register y 0x8005.f044 tictrl 8 0x0 tick control register y 0x8005.f048 ticnt 8 0x0 tick count register y 0x8005.f04c tibase 8 0xff tick base register y 0x8005.f060 protctrl 1 0x1 write protection control register - 0x8005.f07c protect1 8 - write protection register 1 (w/o) - 0x8005.f064 protect2 8 - write protection register 2 (w/o) - 0x8005.f078 protect3 8 - write protection register 3 (w/o) - 0x8005.f06c protectlast 8 - write protection register last (w/o) - 0x8005.f068 rtctrlreset 1 0x0 control register reset register -
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 246 - 9.11.2.1 rtc reset register (rtctrlreset) 0x8005.f068 7 6 5 4 3 2 1 0 ctrlreset bits type function 7:1 - reserved 0 w reset bit to initialize the rtc control register if you use the rtc for the first time, you should set this bit first of all. if this bit is set to ?1?, the rtc control register will be cleared. notice: only inten & evten bits in the rtc control register are initialized by the system reset si gnal. 1: reset 9.11.2.2 rtc protection enable register (protctrl) 0x8005.f064 7 6 5 4 3 2 1 0 protecten bits type function 7:1 - reserved 0 r/w write protection enable when this bit set to ?1? , wirte protection setup flow is started. to release write protection, user should write some fixed value into rtc protection data registers sequentially. 0: no write avaliable to another register 1: wirte protection enable note the specific description is in chapter 9.11.3.6 write operation
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 247 - 9.11.2.3 rtc protection 1,2,3,last register (protect 1,2,3,last) 0x8005.f07c / 0x8005.f064 / 0x8005.f078 / 0x8005.f06c 7 6 5 4 3 2 1 0 protect data [7:0] bits type function 7:0 w protect data note the specific description is in chapter 9.11.3.6 write operation 9.11.2.4 rtc control register (rtctrl) 0x8005.f000 7 6 5 4 3 2 1 0 evten inten clksel reset rtc stop bits type default function 7:6 - - reserved 5 r/w 0 rtc event enable. if this bit is set high, the event signal could be sent to pmu for using as a wake-up signal. there is no need for the event signal to set the inten bit 0: rtc event disable 1: rtc event enalbe 4 r/w 0 rtc interrupt enable when rtc count register value meets rtc alarm register?s, alarm interrupt is generated. 0: interrupt disable 1: interrupt enable 3 - - reserved 2 r/w 0 rtc clock select if this bit set high, rtc clock source will be connneted to 32768khz only for test 0: rtc clock is 1hz 1: rtc clock is 32768hz 1 r/w 0 rtc counter register reset if this bit is set high, rtc counter register will be cleared. although this bit is 1, the rtc clock still alive. 0: no reset 1: rtc cnt register reset 0 r/w 1 rtc start / stop if this bit is set high, a 32khz clock isn?t supplied to the clock divider, and then a clk1hz isn?t made. 0: rtc start 1: rtc stop
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 248 - 9.11.2.5 rtc status register (rtcstat) 0x8005.f004 7 6 5 4 3 2 1 0 tick flag read flag alm flag bits type function 7:3 - reserved 2 r tick interrupt status flag interrupt signal is generated when ticnt register value meets tibase register value. read only valid and writing this bit to ?1? clears this flag. 0: interrupt was not generated or was cleared. 1: interrupt was generated. 1 r read status flag if this bit is set, rtc cnt register value is copied into the copy reigster internally. the system could read the wished value in the copy register. read only valid and writing this bit to ?1? clears this flag. 0: read flag was not generated or was cleared. 1: read flag was generated. 0 r alarm interrupt status flag alarm event interrupt flag is set when the rtc register values equal to the contents of the alarm register. read only valid and writing this bit to ?1? clears this flag. an interrupt is continued for one second. after generating an interrupt, you have to clear alarm enable bit in alctrl register before clearing the status bit. if the status bit is just only set low before going by 1 second, an interrupt is made again. 0: interrupt was not generated or was cleared. 1: interrupt was generated. 9.11.2.6 rtc second register (rtcsec) data in rtc counter registers is interpreted in bcd format. for example, if the second register contains 0101[6:4] 1001[3:0], then the contents are interpreted as the value 59 seconds. 0x8005.f008 7 6 5 4 3 2 1 0 rtcsec10 [6:4] rtcsec1 [3:0] bits type function 7 - reserved 6:4 r/w value for 10 seconds unit from 0 to 5 3:0 r/w value for second unit from 0 to 9
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 249 - 9.11.2.7 rtc minute register (rtcmin) 0x8005.f00c 7 6 5 4 3 2 1 0 rtcmin10 [6:4] rtcmin1 [3:0] bits type function 7 - reserved 6:4 r/w value for 10 minutes unit from 0 to 5 3:0 r/w value for minute unit from 0 to 9 9.11.2.8 rtc hour register (rtchor) hour register contents are values expressed in 24 hour mode. 0x8005.f010 7 6 5 4 3 2 1 0 rtchor10 [5:4] rtchor1 [3:0] bits type function 7:6 - reserved 5:4 r/w value for 10 hours unit from 0 to 2 3:0 r/w value for hour unit from 0 to 9 9.11.2.9 rtc day register (rtcday) 0x8005.f014 7 6 5 4 3 2 1 0 rtcday10 [5:4] rtcday1 [3:0] bits type function 7:6 - reserved 5:4 r/w value for 10 days unit from 0 to 3 3:0 r/w value for day unit from 0 to 9 9.11.2.10 rtc month register (rtcmon) 0x8005.f018 7 6 5 4 3 2 1 0 rtcmon10 rtcmon1 [3:0] bits type function 7:5 - reserved 4 r/w value for 10 months unit from 0 to 1 3:0 r/w value for month unit from 0 to 9
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 250 - 9.11.2.11 rtc year register (rtcyer) leap-year adjustment is automatic for year 2000 to 2099 0x8005.f01c 7 6 5 4 3 2 1 0 rtcyer10 [7:4] rtcyer1 [3:0] bits type function 7:4 r/w value for 10 years unit from 0 to 9 3:0 r/w value for year unit from 0 to 9 9.11.2.12 rtc day of week register (rtcwek) the day-of-week register contains values representing the day of week as shown in the following table. 0x8005.f020 7 6 5 4 3 2 1 0 rtcwek [2:0] bits type function 7:3 - reserved 2:0 r value for weekday unit from saturday to friday bit 2 bit 1 bit 0 day of week 0 0 0 saturday 0 0 1 sunday 0 1 0 monday 0 1 1 tuesday 1 0 0 wednesday 1 0 1 thursday 1 1 0 friday
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 251 - 9.11.2.13 rtc alarm control register (alctrl) 0x8005.f024 7 6 5 4 3 2 1 0 alen alweken alyeren almonen aldayen alhorem alminen alsecen bits type function 7 r/w alarm enable an interrupt is continued for one second. after generating an interrupt, you have to clear alarm enable bit before clearing the status bit. if the status bit is just only set low before going by 1 second, an interrupt is made again. 0: alarm function disable 1: alarm function enable 6 r/w alarm day of week enable 0: disable 1: enable 5 r/w alarm year enable 0: disable 1: enable 4 r/w alarm month enable 0: disable 1: enable 3 r/w alarm day enable 0: disable 1: enable 2 r/w alarm hour enable 0: disable 1: enable 1 r/w alarm minute enable 0: disable 1: enable 0 r/w alarm second enable if this bit is set to ?0?, the alarm interrupt is generated at ?00? second. 0: disable 1: enable 9.11.2.14 rtc alarm second register (alsec) 0x8005.f028 7 6 5 4 3 2 1 0 alsec10 [6:4] alsec1 [3:0] bits type function 7 - reserved 6:4 r/w value for 10 seconds unit from 0 to 5 3:0 r/w value for second unit from 0 to 9
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 252 - 9.11.2.15 rtc alarm minute register (almin) 0x8005.f02c 7 6 5 4 3 2 1 0 almin10 [6:4] almin1 [3:0] bits type function 7 - reserved 6:4 r/w value for 10 minutes unit from 0 to 5 3:0 r/w value for minute unit from 0 to 9 9.11.2.16 rtc alarm hour register (alhor) 0x8005.f030 7 6 5 4 3 2 1 0 alhor10 [5:4] alhor1 [3:0] bits type function 7:6 - reserved 5:4 r/w value for 10 hours unit from 0 to 2 3:0 r/w value for hour unit from 0 to 9 9.11.2.17 rtc alarm day register (alday) 0x8005.f034 7 6 5 4 3 2 1 0 alday10 [5:4] alday1 [3:0] bits type function 7:6 - reserved 5:4 r/w value for 10 days unit from 0 to 3 3:0 r/w value for day unit from 0 to 9 9.11.2.18 rtc alarm month register (almon) 0x8005.f038 7 6 5 4 3 2 1 0 almon10 almon1 [3:0] bits type function 7:5 - reserved 4 r/w value for 10 months unit from 0 to 1 3:0 r/w value for month unit from 0 to 9
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 253 - 9.11.2.19 rtc alarm year register (alyer) 0x8005.f03c 7 6 5 4 3 2 1 0 a lyer10 [7:4] alyer1 [3:0] bits type function 7:4 r/w value for 10 years unit from 0 to 9 3:0 r/w value for year unit from 0 to 9 9.11.2.20 rtc alarm day of week register (alwek) the day-of-week register contains values representing the day of week as shown in the following table. 0x8005.f040 7 6 5 4 3 2 1 0 alwek [2:0] bits type function 7:3 - reserved 2:0 r/w value for weekday unit from saturday to friday bit 2 bit 1 bit 0 day of week 0 0 0 saturday 0 0 1 sunday 0 1 0 monday 0 1 1 tuesday 1 0 0 wednesday 1 0 1 thursday 1 1 0 friday
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 254 - 9.11.2.21 rtc tick timer control register (tictrl) 0x8005.f044 7 6 5 4 3 2 1 0 tinten clksel [5:4] npwdn cntreset cntrepeat cnten bits type function 7 - reserved 6 r/w tick timer interrupt enable 0: interrupt disable 1: interrupt enable 5:4 r/w tick timer source clock select 00: 256hz 01: 512hz 10: 1024hz 11: 2048hz 3 r/w tick timer power down mode if this bit is set to ?1?, source clock is not connected into tick timer. 0: normal mode 1: power down mode 2 r/w tick timer count register reset 0: no reset 1: counter register reset 1 r/w tick timer repeat mode 0 r/w tick timer count enable 0: stop count 1: start count 9.11.2.22 rtc tick timer count register (ticnt) 0x8005.f048 7 6 5 4 3 2 1 0 ticnt [7:0] bits type function 7:0 r tick time count value from 0 to 255 9.11.2.23 rtc tick timer base register (tibase) 0x8005.f04c 7 6 5 4 3 2 1 0 tibase [7:0] bits type function 7:0 r/w tick time base value from 0 to 255
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 255 - 9.11.3 operation 9.11.3.1 read/write operation to read and write the register in rtc, bit 0 of the rtctrl register must be set. to display calendar and present time, you (or cpu) should read the data in rtcsec, rtcmin, rtchor, rtcday, rtcwek, rtcmon, rtcyer registers respectively. 9.11.3.2 leap year generator this block can determine whether the last date of each month is 28,29,30,31. it is based on data from rtcday, rtcmon and rtcyer registers. 9.11.3.3 alarm function alarm can be set for year, month, day, weekday, hour, minute, and second. alarm function is operated in normal mode or power down mode. in power down (deep sleep) mode, the rtc generates wake-up signal (pwakup) for activating cpu when alarm data is same with rtc data. the rtc alarm control register (alctrl) determines the alarm enable and the condition of the alarm time setting. an interrupt is continued for one second. after generating an interrupt, you have to clear alarm enable bit in alctrl register before clearing the status bit in rtcstat register. if the status bit is just only set low before going by 1 second, and interrupt is made again 9.11.3.4 backup battery operation when the system down, the rtc must be divided on the cpu. after that the rtc operates by using the backup battery. 9.11.3.5 tick time interrupt for interrupt request, the rtc includes tick time counter block, tick time counter can count value up to 255 (tick input frequency is optional. 2048/1024/512/256hz) the tick timer also offers interrupt capability including a periodic interval timer.
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 256 - 9.11.3.6 write operation: protection rtc write operation flow ? protection write enable ? set high to the ctrlreset bit in rtctrlreset register ? set low to the ctrlreset bit in rtctrlreset register ? set high to the reset bit in rtctrl register ? set low to the reset bit in rtctrl register ? rtc register setup ? set low to the rtcstop bit in rtctrl register for starting ? protection write disable *write enable: protctrl ?high? ? protect1 ?8?haa? ? protect2 ?8?h48? ? protect3 ?8?h61? ? protectlast ?8?h99? ? write enable *write disable: protctrl ?low? ? write disable protctrl(0x8005.f060) = 0x1 write disable write idle protect1 protect2 protect3 write enable protect 1st protect 2nd protect 3rd !(protect en) protect last protect en protect 1 (0x8005.f07c) = 0xaa protect 2 (0x8005.f064) = 0x48 protect 3 (0x8005.f078) = 0x61 protect last (0x8005.f06c) = 0x99 protctrl(0x8005.f060) = 0x0 write enable write disable protect en : protect 1st : protect 2nd : protect 3rd : protect last : !(protect en) : protctrl(0x8005.f060) = 0x1 write disable write idle protect1 protect2 protect3 write enable protect 1st protect 2nd protect 3rd !(protect en) protect last protect en protect 1 (0x8005.f07c) = 0xaa protect 2 (0x8005.f064) = 0x48 protect 3 (0x8005.f078) = 0x61 protect last (0x8005.f06c) = 0x99 protctrl(0x8005.f060) = 0x0 write enable write disable protect en : protect 1st : protect 2nd : protect 3rd : protect last : !(protect en) : figure 9-10 write protection diagram
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 257 - 9.11.3.7 read operation read register: one of them - rtcsec, rtcmin, rtchor, rtcday, rtcmon, rtcyer, rtcwek ? rtcstat[1] ?high? ? after reading rtc register (sec~wek), rtcstat[1] should be cleared. ? if you read rtc register without clearing it, you will be given old values. 9.11.3.8 rtc setup flow rtc initialization flow ? protection write enable (refer to chapter 9.11.3.6 write operation) ? set high to the ctrlreset bit in rtctrlreset register ? set low to the ctrlreset bit in rtctrlreset register ? set high to the reset bit in rtctrl register ? set low to the reset bit in rtctrl register ? protection write disable (refer to chapter 9.11.3.6 write operation) rtc operation flow ? protection write enable (refer to chapter 9.11.3.6 write operation) ? set high the rtcstop bit in rtctrl register for rtc stop ? set rtc count registers ? rtcsec/min/hor/day/mon/yer ? set alarm control register ? set alarm time registers to wished value ? alsec/min/hor/day/mon/yer/wek ? select the evten, inten, clksel bits in rtctrl register ? set low the rtcstop bit in rtctrl register for starting rtc ? protection write disable (refer to chapter 9.11.3.6 write operation) tick timer operation flow ? protection write enable (refer to chapter 9.11.3.6 write operation) ? set low the rtcstop bit in rtctrl register ? set tibase reigster to wished value ? select the tinten, clksel[1:0], cntrepeat bits in tictrl register ? set the cnten bit in tictrl register for starting tick timer ? protection write disable (refer to chapter 9.11.3.6 write operation)
amba peripherals (rtc) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 258 -
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 259 - 9.12 2-wire serial bus interface the 2-wire serial bus interface (2-wire sbi) is used to communicate external 2-wire sbi compliant devices such as serial rom or serial display device, etc. it supports both master and slave operation. the 2-wire sbi protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (scl) and one for data (sda). the only external hardware needed to implement the bus is a single pull-up resistor for each of the 2-wire sbi lines. all devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the 2-wire sbi protocol. the main features of 2-wire sbi are : ? only 2 lines needed to communicate ? master and slave operation ? programmable transfer bit rate at master mode (up to 400 khz data transfer speed) ? independently programmable mask of interrupts ? multi-master capability ? device can operate as transmitter or receiver ? only 7-bit addressing is available apb i/f test logic paddr pdata psel scl sda transmitter / receiver input sync. control bit counter / baud generator registers int figure 9-46. block diagram of 2-wire sbi
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 260 - 9.12.1 external signals pin name type description scl i/o serial clock line scl serial clock signal pin. pull-up this pin (open-drain) sda i/o serial data line sda serial data signal pin. pull-up this pin (open-drain) refer to figure 2-1. 208 pin diagram. 9.12.2 registers address name width default description 0x8006.0000 datareg 8 0x0 2-wire sbi data register 0x0806.0004 targetreg 8 0x0 2-wire sbi target slave address register 0x8006.0008 statusreg 16 0x0 2-wire sbi status register 0x8006.000c slavereg 7 0x0 2-wire sbi slave mode address register 0x8006.0010 intmaskreg 8 0x0 2-wire sbi interrupt mask register 0x8006.0014 configreg 8 0x0 2-wire sbi configuration register 0x8006.0018 baudreg 8 0xf 2-wire sbi baud rate control register table 9-16. 2-wire sbi?s register summary
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 261 - 9.12.2.1 2-wire sbi data register (datareg) 0x8006.0000 7 6 5 4 3 2 1 0 data[7:0] bits type function 7:0 r/w data to be transferred in transmit mode, datareg contains the next byte to be transmitted. in receive mode, the datareg contains the last byte received. it is writable while the 2-wire sbi is not in the process of shifting a byte. this occurs when the 2-wire sbi interrupt flag (bit that can be interrupt source in configreg) is set by hardware. the data in datareg remains stable as long as interrupt is set. 9.12.2.2 2-wire sbi target slave register (targetreg) 0x8006.0004 7 6 5 4 3 2 1 0 target addr[6: 0] r/w bits type function 7:1 r/w target slave?s address these bits are the 1 st data to be transmitted in the master mode and not needed in the slave mode. these bits are slave device?s address. 0 r/w read or write this bit specifies transfer direction. when this value is ?1?, master request slave to transmit data (master rx) and when ?0?, master transmits data to slave device(master tx). 0 = master is operating as transmitter. (default) 1 = master is operating as receiver.
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 262 - 9.12.2.3 2-wire sbi status register (statusreg) 0x8006.0008 15 14 13 12 11 10 9 8 - - - - - - - transmitt er 7 6 5 4 3 2 1 0 trans req stopreq eotreq datareq buslost busbusy ack receive master bits type function 15-9 r reserved. 8 r 2-wire sbi is transmitter if this bit is set, it indicates that 2-wire sbi operates as a transmitter. 0 = operates as a receiver unit. (default) 1 = operates as a transmitter unit. 7 r serial transfer requested this bit is set when serial communication is started by other external master and the 2-wire sbi of HMS30C7210 is addressed by the master. this bit can be an interrupt source and is cleared by writing any value to statusreg. 0 = status is cleared or 2-wire sbi is not a slave module. (default) 1 = 2-wire sbi is addressed by winning master. 6 r stop condition this bit is set when abnormal stop condition is detected during data transmission and can be an interrupt source. this bit is cleared by writing any value to statusreg. 0 = status is cleared or normal stop condition is detected. (default) 1 = serial communication is terminated abnormally. 5 r end of transmission condition this bit is set when serial communication is ended by normal stop condition and can be an interrupt source. this bit is cleared by writing any value to statusreg. 0 = status is cleared or serial communication is in progress. (default) 1 = serial communication is terminated normally. 4 r data request after one byte of data is transferred on serial data line (sda), this bit is set for 2-wire sbi to prepare another byte of data (2-wire sbi is a transmitter) or to read the received data (2-wire sbi is a receiver). this bit can be an interrupt source and is cleared by writing any value to statusreg. 0 = status is cleared or serial communication is over. (default) 1 = prepare another byte of data or read the received data in datareg. 3 r bus lost event generated this bit is set when 2-wire sbi lost mastership during arbitration (master mode) or there is no slave device addressed by 2-wire sbi. this bit can be an interrupt source and is cleared by writing any value to statusreg. 0 = status is cleared or 2-wire sbi grant the ownership of serial bus lines. (default) 1 = bus losing condition is generated. 2 r bus is busy now this bit is set while serial communication is going on. 0 = serial bus is idle, in this case any bus master can issue a start condition. (default) 1 = serial bus is used by 2-wire sbi unit now. 1 r ack status this bit is set if the sda line is pulled low by addressed slave device after address cycle, or by a receiver acknowledges after data cycle. 0 = no ack is received. (default) 1 = ack is received. 0 r 2-wire sbi is master indicates whether 2-wire sbi is configured as master or slave. 0 = 2-wire sbi is a slave or the serial bus is idle. (default) 1 = 2-wire sbi is a master. the transreq, datareq, stopreq, eotreq and buslost bits in this
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 263 - register are the source of 2-wire sbi unit?s interrupt. when 2-wire sbi requests an interrupt, the handler reads or writes data according to the transmitter bit and clear the interrupt by writing statusreg. or in receiver mode, the 2-wire sbi can terminate serial communication by giving no ack signal at ack cycle. this can be done by writing singlebyte bit before last data packet. serial communication via 2- wire serial bus is over when buslost, stopreq or eotreq bit is set. in this case, the handler must read the statusreg after writing statusreg. 9.12.2.4 2-wire sbi slave mode address register (slavereg) 0x8006.000c 7 6 5 4 3 2 1 0 - slave address[6:0] bits type function 7 - reserved 6:0 r/w slave address of 2-wire sbi itself when 2-wire sbi is configured as slave device, this register contains the slave address of 2-wire sbi itself. 9.12.2.5 2-wire sbi interrupt mask register (intmaskreg) 0x8006.0010 7 6 5 4 3 2 1 0 - - - transreq mask stopreq mask eotreq mask datareq mask buslost mask bits type function 7-5 - reserved 4 r/w transreq interrupt mask if this bit is set, tranreq interrupt is masked, so no interrupt is requested. 0 = transreq interrupt is enabled. (default) 1 = transreq interrupt is disabled. 3 r/w stopreq interrupt mask if this bit is set, stopreq interrupt is masked, so no interrupt is requested. 0 = stopreq interrupt is enabled. (default) 1 = stopreq interrupt is disabled. 2 r/w eotreq interrupt mask if this bit is set, eotreq interrupt is masked, so no interrupt is requested. 0 = eotreq interrupt is enabled. (default) 1 = eotreq interrupt is disabled. 1 r/w datareq interrupt mask if this bit is set, datareq interrupt is masked, so no interrupt is requested. 0 = datareq interrupt is enabled. (default) 1 = datareq interrupt is disabled. 0 r/w buslost interrupt mask if this bit is set, buslost interrupt is masked, so no interrupt is requested. 0 = buslost interrupt is enabled. (default) 1 = buslost interrupt is disabled.
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 264 - 9.12.2.6 2-wire sbi configuration register (configreg) 0x8006.0014 7 6 5 4 3 2 1 0 restart - soft reset single byte - multi byte force stop start bits type function 7 r/w restart condition (master only) when 2-wire sbi is configured as master, setting this bit transmits a restart condition. 0 = no action is done. (default) 1 = restart condition is generated. 6 - reserved 5 r/w software reset command setting this bit resets 2-wire sbi module and this bit is auto-cleared. 0 = normal operation. (default) 1 = software reset command is issued. 4 r/w single byte is remained this bit is used in 2 cases. i) if only one byte of data is to be transferred, setting this bit with start bit completes serial communication. ii) if more than one byte of data(n bytes) are to be transferred, set this bit after (n-1) bytes are transferred to terminate serial communication. 0 = indicates more than one byte of data are remained when multibyte bit is set. (default) 1 = serial communication is terminated after next data cycle. 3 - reserved 2 r/w multiple bytes transfer (master only) when more than one bytes are to be transferred, set this bit. 0 = only one byte of data is to be transferred. (default) 1 = multiple bytes are to be transferred. 1 r/w forces stop condition if this bit is set, the stop condition is transmitted during data cycle. that is data transfer is terminated abnormally. 0 = no action is done. (default) 1 = stop condition is generated during data cycle. 0 r/w start condition (master only) 2-wire sbi is a master device and initiates a serial communication. 0 = 2-wire sbi is a slave device or no action is done. (default) 1 = start condition is generated. 9.12.2.7 2-wire sbi baud rate control register (baudreg) 0x8006.0018 7 6 5 4 3 2 1 0 baudrate[7:0] bits type function baud rate control the serial clock (scl) rate is determined as f pclk /(2*(baudrate+1)), where f pclk is the frequency of peripheral clock, pclk. to operate correctly, the baudrate value should be greater than 3. baud rate (decimal) divider value scl rate 7:0 r/w 03 f pclk /8 460 khz 04 f pclk /10 369 khz 10 f pclk /22 168 khz 17 f pclk /36 102 khz
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 265 - 9.12.3 operation both sda and scl are bi-directional lines and connected to the positive supply voltage through pull-up resistors. the bus drivers of all 2-wire sbi-compliant devices are open-drain or open-collector. this implements a wired-and function which is essential to the operation of the interface. a low level on a 2-wire sbi bus line is generated when one or more devices output a zero. a high level is output when all 2- wire sbi devices release bus line, allowing the pull-up resistors to pull the line high. below figure depicts general form of connecting more than two devices to the serial bus. device 1 scl sda device 2 device 3 ...... device n vcc r1 r2 figure 9-47. connection of devices to the 2-wire serial bus
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 266 - 9.12.3.1 transferring bits on 2-wire serial bus each data bit transferred on 2-wire serial bus is accompanied by a pulse on the clock line, scl. the level of the data line must be stable when the clock line is high. the only exception to this rule is for generating start and stop conditions. sda scl data stable data change figure 9-48. data validity 9.12.3.2 start and stop conditions of 2-wire sbi the master initiates and terminates a data transfer. the serial communication is initiated when the master issues a start condition on the bus, and it is terminated when the master issues a stop condition. between a start and a stop condition, the bus is considered busy, and no other master is allowed to try to gain the ownership of the bus. sda scl s start condition p stop condition figure 9-49. start and stop conditions before stop condition is detected, a master device can issue a restart condition which is identical to start condition and is symbolized as sr.
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 267 - 9.12.3.3 multi-master bus systems, arbitration and synchronization the 2-wire sbi protocol allows bus systems with several masters. special concerns have been taken in order to ensure that transmissions will proceed as normal, even if more than two masters initiate transmission at the same time. in that case, two problems arise in multi-master bus systems : ? an algorithm must be implemented allowing only one of the masters to complete the transmission. all other masters must stop transmission when they know that they have lost the bus ownership. this process is called arbitration. when a contending master finds out that it has lost the arbitration process, it must immediately switch to slave mode to check whether it is being addressed by the winning master. the fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e., the data being transferred on the bus must not be corrupted. ? different masters may use different scl frequencies. a scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed. the wired-anding of the bus lines is used to solve both these problems. the serial clocks from all masters will be wired-and ed, yielding a combined clock with a high period equal to the one from the master with the shortest high period. the low period of the combined clock is equal to the low period of the master with the longest low period. note that all masters checks the scl line, effectively starting to count their scl high and low time-out periods when the combined scl line goes high or low, respectively. scl from master a scl from master b scl bus line masters a, b start counting low period ta low ta high tb low tb high masters a, b start counting high period figure 9-50. scl synchronization between multiple masters arbitration is carried out by all masters continuously monitoring the sda line after outputting data. if the value read from the sda line does not match the value the master had output, it has lost the arbitration. note that a master can only lose arbitration when it outputs a high sda value while another master outputs a low value. the losing master must immediately go to slave mode, checking if it is being
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 268 - addressed by the winning master. the sda line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. arbitration will continue until only one master remains, and this may take many bits. if several masters are trying to address the same slave, arbitration will continue into the data packet. sda from master a sda from master b sda line synchronized scl line s start condition master a loses arbitration, sda a sda figure 9-51. arbitration between two masters during serial communication, the arbitration procedure is still in progress at the moment when a restart condition or a stop condition is transmitted to the serial bus. if it?s possible for such a situation to occur, the masters involved must send this restart condition or stop condition at the same position in the format frame. in other words, arbitration is not allowed between : ? a restart condition and a data bit ? a stop condition and a data bit ? a restart condition and a stop condition. slaves are not involved in the arbitration procedure.
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 269 - 9.12.3.4 serial communication the data transfer on 2-wire serial bus is performed as depicted in the following figure. first, the master device examines the serial bus lines are available. when the serial bus is not busy, the master transmits a start condition and the first data packet which are composed of 7 address bits and, one read/write control bit. and then, the slave device addressed by the master device acknowledges by pulling sda line low in the ninth scl cycle (ack cycle). if the addressed slave device does not exist or is busy doing other tasks, the serial communication is terminated and the sda line is left high in the ack cycle. sda scl s or sr msb ack 12 7 8 9 12 3 - 8 9 ack from slave device end of byte transfer slave generates interrupt scl is held low until interrupt is handled ack from a receiver start or restart stop or restart ack sr or p p sr figure 9-52. address and data packet of 2-wire sbi after data transfer is ended, the master transmits a stop condition or restart condition. note that between a start and a stop condition, all data packet is composed of 8 bits data and one ack bit. the first data packet after a start or restart condition is an address packet which is composed of 7 address bits and one r/w control bit. and all address and data packets are transmitted msb first. a transfer is basically consists of a start condition, a address packet, one or more data packets and a stop condition. address cycle is the cycle while address packet is transferred and data cycle is the c ycle while data packet is transferred. and address packet is the 1 st 9-bit data after start condition, and data packets are 9-bit data consisting of 8-bit data byte and one bit ack . either in address or data cycle, the master generates the clock and start and stop conditions, while the receiver is responsible for acknowledging the reception. an acknowledge, ack is signaled by the receiver pulling the sda line low during the ninth scl cycle. if the receiver leaves the sda line high, a nack is signaled. when the receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the transmitter by sending a nack after the final byte.
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 270 - sda output (transmitter) sda output (receiver) scl (master) s ack 1 ack start condition 2 8 9 no ack figure 9-53. ack signal generation in HMS30C7210, the address packet comes from targetreg when configured as master mode. and there are 4 operating modes internally according to transfer direction and bus mastership. the individual operating sequence is stated below. all cases are stated assuming interrupt mode operation.
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 271 - master transmitter ? decide target slave device to which 2-wire sbi wants to transmit data and write 7-bit address and 1-bit r/w control bit to targetreg. the value written in targetreg is the 1 st 8-bit data (address packet) to be transmitted. ? configure baudreg to select scl frequency. ? write 2 nd 8-bit data (1 st data packet) to transmit to datareg. ? enable interrupt sources by writing in tmaskreg. assume all interrupt sources are enabled through out this sequence. ? generate start condition. this is done by setting both start bit and multibyte bit in configreg. if only one byte of data is need to be transmitted, set both the start bit and singlebyte bit in configreg. in this case, an eot interrupt is requested after 1 st data packet and the below steps are needless. ? wait ack from addressed slave after transmitting address packet consisting of 7- bit address and 1-bit r/w control bit. step 6 is done by 2-wire sbi unit not by software. ? if 2-wire sbi receives an ack for address packet, the 1 st data packet is transmitted and datareq interrupt is requested. the interrupt handler prepares next data to transmit and write status register to clear interrupt and proceed to data cycle. and then wait next datareq interrupt. if no ack is signaled for address packet, serial communication is terminated and buslost interrupt is requested. in this case, read statusreg to release serial bus after writing statusreg. ? if 2-wire sbi receives an ack for data packet, datareq interrupt is requested. the interrupt handler writes next data to transmit into datareg and clears interrupt by writing statusreg. termination of serial communication is done in 2 ways. one method is by software decision. if there are n bytes of data packet to transmit, software sets singlebyte bit in configreg after (n-1)th data packets are transmitted. while changing configreg, start bit must preserve previous value and multibyte bit must be cleared simultaneously. the other method is based on ack signal. if no ack for data packet is received, serial communication is terminated and an eot interrupt is requested. in both cases, read statusreg to release serial bus after writing statusreg. repeat step 8 until serial communication is over. the above steps are normally used when 2-wire sbi is configures as master transmitter. even if ack for a data packet is received, serial communication can be terminated by setting stop bit in configreg. the next figure depicts above steps. a6 a5 a4 a3 a2 a1 a7 a7 d7 d6 d5 d4 d3 d2 d1 d7 d7 d6 d5 d4 d3 d2 d1 d0 d0 sda scl int s p [m]address transmit [m]transmitter [s]generate ack [m]data transmit [s]generate ack [m]data transmit [s]no ack stop condition prepare data to transmit and write statusreg to clear datareq interrupt figure 9-54. waveform when 2-wire sbi is master transmitter in the above figure, the symbol int represents an interrupt from 2-wire sbi and [m] represents signal generated from master, [s ] represents signal generated by slave.
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 272 - master receiver ? decide target slave device from which 2-wire sbi wants to receive data and write 7-bit address and 1-bit r/w control bit to targetreg. the value written in targetreg is the 1 st 8-bit data (address packet) to be transmitted. ? configure baudreg to select scl frequency. ? enable interrupt sources by writing in tmaskreg. assume all interrupt sources are enabled through out this sequence. ? generate start condition. this is done setting both start bit and multibyte bit in configreg. if only one byte of data is need to be received, set both the signlebyte bit and start bit in configre g. in this case, an eot interrupt is requested after 1 st data packet and the below steps are needless. ? wait ack from addressed slave after transmitting address packet consisting of 7- bit address and 1-bit r/w control bit. ? if 2-wire sbi receives an ack for address packet, the 1 st data packet is received and datareq interrupt is requested. the interrupt handler prepares next data to transmit and write any value statusreg to clear interrupt and proceed to data cycle. and then wait next datareq interrupt. if no ack is signaled for address packet, serial communication is terminated and buslost interrupt is requested. in this case, read statusreg to release serial bus after writing statusreg. ? when datareq interrupt is r equested, 2-wire sbi reads the datareg which contains the recently received 8-bit data packet. if there?re more data to be received from the slave, the interrupt handler need only to clear interrupt by writing the statusreg. but if next data packet is the last data packet or 2-wire sbi can?t receive more than one data for some reason, 2-wire sbi signals no ack at the next data packet by setting the singlebyte bit in configreg. while changing configreg, start bit must preserve previous value and multibyte bit must be cleared simultaneously. when 2-wire sbi compliant transmitter does not receive an ack at ack cycle, the serial communication ends automatically and the 2-wire sbi of HMS30C7210 request an eot interrupt. in this case, read statusreg to free serial bus after writing statusreg. repeat step 7 until serial communication is over. the above steps are normally used when 2-wire sbi is configures as master receiver. the next figure depicts above steps. a6 a5 a4 a3 a2 a1 a7 a7 d7 d7 d6 d5 d4 d3 d2 d1 d7 d7 d6 d5 d4 d3 d2 d1 d0 d0 sda scl int s p [m]receiver [s]generate ack [m]address transmit [s]data transmit [s]data transmit [m]generate ack [m]no ack read received data and write statusreg to clear datareq interrupt stop condition figure 9-55. waveform when 2-wire sbi is master receiver in the above figure, the symbol int represents an interrupt from 2-wire sbi and [m] represents signal generated from master, [s ] represents signal generated by slave.
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 273 - slave transmitter ? enable interrupt sources by writing in tmaskreg. assume all interrupt sources are enabled through out this sequence. by default, transreq interrupt must be enabled to use interrupt mode. ? wait for start condition from external master device. ? if 7-bits address of address packet matches slavereg, ack signal for address packet is transmitted and transreq interrupt is requested. when transreq interrupt is requested, read the statusreg and verify that the master requires data from 2-wire sbi by checking the transmitter bit in statusreg. ? write the 1 st data into datareg and clear interrupt by writing statusreg. ? after transmitting data packet, 2-wire sbi checks the ack signal at ack cycle. if no ack is received, the serial communication ends and an eot interrupt is requested. in this case, read statusreg to release serial bus after writing statusreg. if ack signal is received, 2-wire sbi requests an datareq interrupt. in this case, write the next data to transmit into datareg and clear interrupt by writing the statusreg. repeat this step until serial communication is over. the above steps are normally used when 2-wire sbi is configures as slave transmitter. the next figure depicts above steps. a6 a5 a4 a3 a2 a1 a7 a7 d7 d6 d5 d4 d3 d2 d1 d7 d6 d5 d4 d3 d2 d1 d0 d0 sda scl int s p [m]address transmit [s]generate ack [m]receiver [s]data transmit [m]generate ack [s]data transmit [m]no ack prepare data to transmit and write statusreg to clear datareq interrupt prepare data to transmit and write statusreg to clear transreq interrupt stop condition figure 9-56. waveform when 2-wire sbi is slave transmitter in the above figure, the symbol int represents an interrupt from 2-wire sbi and [m] represents signal generated from master, [s ] represents signal generated by slave.
amba peripherals (2-wire sbi) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 274 - slave receiver ? enable interrupt sources by writing in tmaskreg. assume all interrupt sources are enabled through out this sequence. by default, transreq interrupt must be enabled to use interrupt mode. ? wait for start condition from external master device. ? if 7-bits address of address packet matches slavereg, ack signal for address packet is transmitted and transreq interrupt is requested. when transreq interrupt is requested, read the statusreg and verify that the master wants to transmit data to 2-wire sbi by checking the transmitter bit in statusreg. ? if no more than one data is acceptable, set the singlebyte bit in configreg to transmit no ack at next data packet, then an eot interrupt is requested and serial communication is over. in this case, step 5 is needless and read the statusreg to release the serial bus after clearing the interrupt by writing the statusreg. or 2-wire sbi is capable of more than one data packet, just clear interrupt by writing statusreg and receive 1 st data. ? when datareq interrupt is r equested, 2-wire sbi reads the datareg which contains the recently received 8-bit data packet. if there?re more data to be received from the master, the interrupt handler need only to clear interrupt by writing the statusreg. but if next data packet is the last data packet or 2-wire sbi can?t receive more than one data for some reason, 2-wire sbi signals no ack at the next data packet by setting the singlebyte bit in configreg. when 2-wire sbi compliant transmitter does not receive an ack at ack cycle, the serial communication ends automatically and the 2-wire sbi of HMS30C7210 request an eot interrupt. in this case, read statusreg to release serial bus after writing statusreg. repeat step 5 until serial communication is over. the above steps are normally used when 2-wire sbi is configures as slave receiver. the next figure depicts above steps. a6 a5 a4 a3 a2 a1 a7 a7 d7 d6 d5 d4 d3 d2 d1 d7 d6 d5 d4 d3 d2 d1 d0 d0 sda scl int s p [s]generate ack [m]transmitter [m]address transmit [m]data transmit [m]data transmit [s]generate ack [s]no ack read received data and write statusreg to clear datareq interrupt write statusreg to clear transreq interrupt stop condition figure 9-57. waveform when 2-wire sbi is slave receiver in the above figure, the symbol int represents an interrupt from 2-wire sbi and [m] represents signal generated from master, [s ] represents signal generated by slave.
amba peripherals (matrix keyboard controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 275 - 9.13 matrix keyboard interface controller the matrix keyboard interface controller is an amba slave module that connects to the advanced peripheral bus (apb). for more information about amba, please refer to the amba specification (arm ihi 0001). the interface controller is designed to communicate with the external keyboard matrix. the keyboard interface uses the pins kscani [5:0] and kscano [5:0]. it is possible to select one of three scan clock frequencies. the main features of keyboard controller are : ? controllable scanning frequency ? maximum 6x6 keyboard matrix is supported ? key value is stored in kbvr0/1 kscani input inversion 2-stage input sample kbsc scan counter scan clock select kscano[5:0] column control kscani[5:0] kbvr0/1 kbsr / interrupt kbdinterrupt period control kbcr apb data bus clock generator figure 9-58. block diagram of keyboard controller
amba peripherals (matrix keyboard controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 276 - 9.13.1 external signals pin name type description kscano [5:0] o column enable signals to keyboard matrix key input is valid only when kscano pin is low. the outputs of kscano pins act like ring counter so as to cover all columns of keyboard matrix. if pins are used for keyboard function, pull- up resistors need to be connected. kscani [5:0] i row inputs from keyboard matrix if pins are used for keyboard function, pull-up resistors need to be connected. normally each kscani line maintains high level because of pull-up resistor so, low input is detected as ?key pressed?. refer to figure 2-1. 208 pin diagram. 9.13.2 registers address name width default description 0x8006.1000 kbcr 8 0x0 keyboard configuration register 0x8006.1004 kbsc 6 0x0 keyboard scan out register 0x8006.100c kbvr0 32 0x0 keyboard value register 0 0x8006.1010 kbvr1 16 0x0 keyboard value register 1 0x8006.1018 kbsr 2 0x0 keyboard status register table 9-17. matrix keyboard interface controller register summary
amba peripherals (matrix keyboard controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 277 - 9.13.2.1 keyboard configuration register (kbcr) 0x8006.1000 7 2 1 0 scan enable npower down clksel bits type function 7 r/w key input scanning enable setting this bit enables key input scanning coming from kscani pins. note that both scanenable and npowerdown bits must be set to start key input scanning. it is recommended that both scanenable and npowerdown bits are cleared to stop key input scanning. it is software's responsi bility to de-bo unce the key pressed information. keyboard interrupt is generated in all pmu states except deep sleep. 0 = stops key input scanning. 1 = starts key input scanning. 6:3 - reserved. keep these bits to zero. 2 r/w power down mode (active low) activates keyboard controller module by supplying pclk. 0 = indicates power down mode and internal operating clock signal is always ?0?. (default) 1 = clock generator unit supplies incoming pclk to keyboard controller module. scan clock select bits this controls the operating clock of scanning matrix keyboard. value scan clock source scan rate 1:0 r/w 00 reserved not available 01 pclk / 128 (28khz) 138 times / sec 10 pclk / 256 (14khz) 69 times / sec 11 pclk / 512 (7khz) 34 times / sec
amba peripherals (matrix keyboard controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 278 - 9.13.2.2 keyboard scan out register(kbsc) 0x8006.1004 5 4 3 2 1 0 scanout bits r/w function 5 r indicates that 1 st column is being scanned. when low, the pressed kscani inputs are stored in kbvr0[29:24]. this bit is directly connected to kscano[5]. 0 = 1 st column is being scanned. (default) 1 = 1 st column is not being scanned. 4 r indicates that 2 nd column is being scanned. when low, the pressed kscani inputs are stored in kbvr0[21:16]. this bit is directly connected to kscano[4]. 0 = 2 nd line will be scanned. (default) 1 = 2 nd column is not being scanned. 3 r indicates that 3 rd column is being scanned. when low, the pressed kscani inputs are stored in kbvr0[13:8]. this bit is directly connected to kscano[3]. 0 = 3 rd line will be scanned. (default) 1 = 3 rd column is not being scanned. 2 r indicates that 4 th column is being scanned. when low, the pressed kscani inputs are stored in kbvr0[5:0]. this bit is directly connected to kscano[2]. 0 = 4 th line will be scanned. (default) 1 = 4 th column is not being scanned. 1 r indicates that 5 th column is being scanned. when low, the pressed kscani inputs are stored in kbvr1[13:8]. this bit is directly connected to kscano[1]. 0 = 5 th line will be scanned. (default) 1 = 5 th column is not being scanned. 0 r indicates that 6 th column is being scanned. when low, the pressed kscani inputs are stored in kbvr1[5:0]. this bit is directly connected to kscano[0]. 0 = 6 th line will be scanned. (default) 1 = 6 th column is not being scanned.
amba peripherals (matrix keyboard controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 279 - 9.13.2.3 keyboard value register (kbvr0) 0x8006.100c 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 st column kscani [5:0] 2 nd column kscani [5:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 rd column kscani [5:0] 4 th column kscani [5:0] bits type function 31:30 r reserved 29:24 r the pressed kscani during kscano[5] is low. kscani[5:0] maps to kbvr0[29:26]. if any pin of kscani[5:0] is low, the corresponding bit position in kbvr0[29:26] becomes ?1? . 0 = kscani input is pressed while kscano[5] is high or no kscani input is pressed while kscano[5] is low. 1 = the corresponding kscani input is pressed. 23:22 r reserved 21:16 r the pressed kscani during kscano[4] is low. kscani[5:0] maps to kbvr0[21:16]. if any pin of kscani[5:0] is low, the corresponding bit position in kbvr0[21:16] becomes ?1? . 0 = kscani input is pressed while kscano[4] is high or no kscani input is pressed while kscano[4] is low. 1 = the corresponding kscani input is pressed. 15:14 r reserved 13:8 r the pressed kscani during kscano[3] is low. kscani[5:0] maps to kbvr0[13:8]. if any pin of kscani[5:0] is low, the corresponding bit position in kbvr0[13:8] becomes ?1? . 0 = kscani input is pressed while kscano[3] is high or no kscani input is pressed while kscano[3] is low. 1 = the corresponding kscani input is pressed. 7:6 r reserved 5:0 r the pressed kscani during kscano[2] is low. kscani[5:0] maps to kbvr0[5:0]. if any pin of kscani[5:0] is low, the corresponding bit position in kbvr0[5:0] becomes ?1? . 0 = kscani input is pressed while kscano[2] is high or no kscani input is pressed while kscano[2] is low. 1 = the corresponding kscani input is pressed.
amba peripherals (matrix keyboard controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 280 - 9.13.2.4 keyboard value register (kbvr1) 0x8006.1010 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5th column kscani [5:0] 6 th column kscani [5:0] bits type function 15:14 r reserved 13:8 r the pressed kscani during kscano[1] is low. kscani[5:0] maps to kbvr1[13:8]. if any pin of kscani[5:0] is low, the corresponding bit position in kbvr0[13:8] becomes ?1? . 0 = kscani input is pressed while kscano[1] is high or no kscani input is pressed while kscano[1] is low. 1 = the corresponding kscani input is pressed. 7:6 r reserved 5:0 r the pressed kscani during kscano[0] is low. kscani[5:0] maps to kbvr1[5:0]. if any pin of kscani[5:0] is low, the corresponding bit position in kbvr0[5:0] becomes ?1? . 0 = kscani input is pressed while kscano[0] is high or no kscani input is pressed while kscano[0] is low. 1 = the corresponding kscani input is pressed. 9.13.2.5 keyboard status register (kbsr) 0x8006.1018 1 0 wakeup keyintr bits type function 7:2 - reserved 1 r wake up status this bit is set if any key is pressed when scanenable in kbcr is low. this bit is a source of keyboard interrupt, which is generated in all pmu states except deep sleep mode. this bit is cleared when non-zero value is written in this register. 0 = key scanning is enabled or no key is pressed when scanenable is low. (default) 1 = there is at least one point pressed at matrix keyboard when scanenable is low. 0 r end of one scan period if one scan period is over, this flag is set and kbvr0/1 contains all the pressed points of matrix keyboard. when this bit is set, a keyboard interrupt is requested. this bit is cleared when non-zero value is written in this register. 0 = kbsr is cleared or key scanning is going on. (default) 1 = indicates that kbvr0/1 are loaded with the value of keys pressed and software should read kbvr0/1 registers.
amba peripherals (matrix keyboard controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 281 - 9.13.3 operation 9.13.3.1 conceptual configuration of keyboard matrix keyboards use a matrix with the rows and columns made up of wires. each key acts like a switch. when a key is pressed, a column wire(called kscano) makes contact with a row wire(called kscani) and completes a circuit. the keyboard controller detects this closed circuit and registers it as a key press. here is a simple keyboard matrix. the symbol kscano and kscani are same as those of HMS30C7210. at reset or when key scanning is not enabled, all kscano lines of HMS30C7210 are low to generate wakeup event in kbsr. kscano[0] [1] [2] [3] [4] [5] kscani[0] kscani[1] kscani[2] kscani[3] kscani[4] kscani[5] vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd vdd sw00 sw10 sw01 sw11 sw44 sw54 sw45 sw55 figure 9-59. keyboard matrix configuration the above keyboard matrix works ?cause only one of kscano lines are low while key scanning is enabled. if a key sw00 is pressed when kscano[0] is low, the keyboard controller detects that kscani[0] input is active. similarly if two keys sw10, sw11 are pressed when kscano[1] is low, the controller detects that kscani[1:0] inputs are active. note that pull-up resistors are connected to kscani and kscano lines. if no switch is pressed, kscani maintain high level and the controller knows that there?s no key input. if any switch is pressed, the corresponding kscani line is changed to low level and the controller knows that there are some keys pressed and stores the position of kscani to kbvr0/ 1 register. the pressed key position is stored as ?1? in kbvr0/1.
amba peripherals (matrix keyboard controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 282 - 9.13.3.2 kscano output timing when scanenable is set, the outputs of keyboard controller, kscano[5:0], acts like ring counter. in other words, during 1 scan period only one of kscano lines is low at one time(column period). this en ables kscani[n] is detected as unique switch during 1 scan period. the following figure shows the output waveform of kscano lines. once scanenable in kbcr is set according to scan rate which is controlled by clksel, kscano[5] is low at 1 st column period and then kscano[4], kscano[3], kscano[2], kscano[1], kscano[0] are low periodically. in 6x6 matrix configuration, only 6 column periods are needed in one scan period. but there are 8 column periods and this makes no problem using keyboard matrix. kscano[5] kscano[4] kscano[3] kscano[2] kscano[1] kscano[0] 1 scan period figure 9-60. kscano output timing
amba peripherals (matrix keyboard controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 283 - 9.13.3.3 scanning rate selection and clock divider the scan rate is controlled by clksel in kbcr. kbcr timing control scanenable npowerdown scan counter clksel scanclk pclk column control period control gatedpclk scan counter figure 9-61. clock divider of keyboard controller like other slow apb peripherals, keyboard controller is clocked by pclk. key scanning is much like mechanic process and pclk is very fast for that purpose. so the main clock of scan counter unit which is used to control column and scan period is scanclk controlled by clksel bits. pclk scanclk kscano[5] kscano[4] 1 column period (26 scanclks) 1 scan period (208 scanclks) figure 9-62. key scan period and column period scanclk is achieved from output of flip-flops(scancounter) which are clocked by pclk. these flip-flops are asynchronously cleared when scanenable is ?0?, and increments by one when scanenable is ?1?. the scancounter is 9-bit(8 to 0) counter and the output is the source of scanclk. 1 column is composed of 26 scanclks and 1 scan period is composed of 8 columns, therefore 1 scan period is composed of 208 scanclks. the following table shows how the scan rate is calculated from clksel. for example, clksel is ?01?, the output of 7 th flip-flop of scancounter counter is the source of
amba peripherals (matrix keyboard controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 284 - scanclk, so divider value becomes ?128? because output of 7 th flip-flop makes 1 clock pulse after 128 pclks. clksel divider f scanclk = f pclk / divider scan rate 01 128 approximately 28 khz 138 times / sec 10 256 approximately 14 khz 69 times / sec 11 512 approximately 7khz 34 times / sec table 9-18. scan rate calculation from clksel 9.13.3.4 scanning sequence of key inputs as stated previously kscani lines are detected pressed only when corresponding kscano line is low. kscano[5] kscano[4] kscano[3] kscano[2] kscano[1] kscano[0] kscanin[5:0] wakeup in kbsr (kbdinterrupt) 0x3f 0x3f any line of kscani is pulled low scanenable and npowerdown are set figure 9-63. wakeup interrupt & key scanning enabled at reset or when key scanning is not enabled, all kscano lines are low. if any switch is pressed wakeup in kbsr is set and interrupt is requested. the keyboard interrupt handler usually enables key scanning by setting both scanenable and npowerdown in kbcr. simultaneously kscano lines start making column period as in the previous figure. the following figure shows example of interrupt handler routine related to keyboard interrupt.
amba peripherals (matrix keyboard controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 285 - kbvr0/1 ready? (keyintr == 1) keyboardhandler reads kbvr0/1 y n y n enable key scanning (scanenable = 1, npowerdown = 1, scanstartflag = 1) kbd interrupt key scanning started ? (scanstartflag == 0) key pressed ? (wakeup == 1) disable key scanning (scanenable = 0, npowerdown = 0, scanstartflat = 0) y y n the symbol means exit handler routine and scanstartflag is ? 0 ? by default n no key pressed during predefined time? figure 9-64. a flow chart of setting keyboard controller the above flow chart can be summarized as follows : ? see if key scanning is started already by checking scanstartflag. if scanstartflag is not set, go to step 4. ? check wakeup in kbsr. (interrupt) ? set scanenable, npowerdown and scanstartflag to enable key scanning and exit handler routine. (kbcr) ? check keyintr in kbsr. (interrupt) ? read kbvr0/1. ? if no key is pressed for predefined time, disable key scanning and exit handler routine. ? to continue key scanning, just exit handler routine and wait next keyboard interrupt.
amba peripherals (matrix keyboard controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 286 - the following figure shows internal timing diagram of keyboard controller. note that low value of kscani is detected as ?key pressed? and stored in kbvr0/1 as binary ?1?. the kscani lines are sampled 2 times during low phase of each kscano line and if 2 sampled values are different, the kscani line is considered as not pressed. 2 times sampling is simplified de-bouncing for input pin kscani lines. when one scan period is over, the keyintr bit in kbsr is set and an interrupt is requested. because the timing of kscano is periodic after scanenable is set, software must handle the requested interrupt by reading kbvr0/1 before kscano[5] of next scan period makes an rising edge. this time limit is symbolized as t int in the following figure. as 26 scanclks makes one column period, t int is approximately 3.7ms when clksel is ?01?. clksel f scanclk t int 01 28 khz approximately 0.9 ms 10 14 khz approximately 1.8 ms 11 7 khz approximately 3.7 ms table 9-19. estimated t intr according to clksel kscano[5] kscano[4] kscano[3] kscano[2] kscano[1] kscano[0] kscanin[5:0] kbvr0[31:0] kbvr1[15:0] keyintr 0x11 1 st sampling of kscani 2 nd sampling of kscani kbvr writing time of current column kbvr1[29:24] kbvr1[21:16] kbvr1[13:8] kbvr1[5:0] kbvr0[13:8] kbvr0[5:0] 0x22 0x33 0x04 0x15 0x26 0x3f 0x2e000000 0x2e1d0000 0x2e1d0c00 0x2e1d0c3b 0x2a00 0x2a19 t int figure 9-65. kbvr0/1 write timing
amba peripherals (matrix keyboard controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 287 - 9.13.3.5 usage and restrictions the maximum size of keyboard matrix that can be used is 6x6(kscani x kscano). but there are some restrictions for kscani pins. the restrictions result in minimum matrix size of 4x1. before using keyboard matrix, pull-up resistors must be connected to kscani and kscano lines that are used for keyboard function. using some of kscano : even if keyboard matrix is connected to HMS30C7210, each kscano line can be configured for gpio. the below table shows possible configuration for kscano pins. the ?o? means kscano[n] can be used for that function (keyboard or gpio) in the table where n is 0,1,2,3,4 or 5. kscano[0] kscano[1] kscano[2] kscano[3] kscano[4] kscano[5] keyboard o (pull-up) o (pull-up) o (pull-up) o (pull-up) o (pull-up) o (pull-up) gpio o o o o o o table 9-20. possible configuration of kscano pins when keyboard matrix is connected
amba peripherals (matrix keyboard controller) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 288 - in the following figure, kscano[3:2] are used for gpios and only kscano[5:4, 1:0] are used for keyboard function. this means that switches sw3x and sw2x(see keyboard matrix configuration figure) ar e ignored and not stored in kbvr0/1 when pressed. note that kscano[3:2] are always high in the figure but these pins can change level ?cause these pins are not connected to keyboard matrix. kscano[5] kscano[4] kscano[3] kscano[2] kscano[1] kscano[0] kscanin[5:0] kbvr0[31:0] kbvr1[15:0] keyintr 0x3e kbvr1[29:24] kbvr1[21:16] kbvr0[13:8] kbvr0[5:0] 0x3f 0x01000000 0x01010000 0x0100 t int figure 9-66. kscano[3:2] are configured for gpio using some of kscani : not like kscano, some kscani pins must be configured for keyboard function to use keyboard matrix. that is, kscani[3:0] must be configured for keyboard function. but kscani[5:4] can be configured for gpio or keyboard function. the below table shows possible configuration for kscani pins. in the table below, the ?o? means kscano[n] can be used for that function (keyboard or gpio) and ?x? means that kscano[n] cannot be used for gpio when keyboard function is enabled where n is 0,1,2,3,4 or 5. kscani[0] kscani[1] kscani[2] kscani[3] kscani[4] kscani[5] keyboard o (pull-up) o (pull-up) o (pull-up) o (pull-up) o (pull-up) o (pull-up) gpio x x x x o o table 9-21. possible configuration of kscani pins when keyboard matrix is connected
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 289 - 9.14 gpio this document describes the programmable input /output module (pio). this is an amba slave module that connects to the advanced peripheral bus (apb). for more information about amba, please refer to the amba specification (arm ihi 0001). most port pins are multiplexed with alternate functions for the peripheral features on the device. how each alternate function interferes with the port pin is described in ?operation? section. refer to the individual module sections for a full description of the alternate function. the i/o status of each port is not changed during ?sleep? or ?deepsleep? mode of pmu. apb i/f pa data paddr psel pdata pstb pwrite bnres deportainput adbnc gpioaint ...... gpioeint pa direction port a port b ...... port d pe data pe direction port e interrupt gen / edge detect interrupt gen / edge detect ...... pa pin control pe pin control deportainput : port a inputs de-bounced by pmu unit adbnc : port a de-bounce enable figure 9-67. block diagram of gpio
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 290 - 9.14.1 external signals pin name type description kscani [5:0] i/o general port a [5:0] kscano [5:0] i/o general port a [11:6] uart5tx i/o general port b [27] uart5rx i/o general port b [26] nudcd i/o general port b [25] nudsr i/o general port b [24] nurts i/o general port b [23] nucts i/o general port b [22] nudtr i/o general port b [21] nuring i/o general port b [20] touchyn i/o general port b [19] touchxn i/o general port b [18] touchyp i/o general port b [17] touchxp i/o general port b [16] gpiob15 i/o general port b [15] gpiob14 i/o general port b [14] irda4tx i/o general port b [13] irda4rx i/o general port b [12] uart3tx i/o general port b [11] uart3rx i/o general port b [10] uart2tx i/o general port b [9] uart2rx i/o general port b [8] scpres[1] i/o general port b [7] scclk[1] i/o general port b [6] scio[1] i/o general port b [5] scrst[1] i/o general port b [4] scpres[0] i/o general port b [3] scclk[0] i/o general port b [2] scio[0] i/o general port b [1] scrst[0] i/o general port b [0] smd[7:0] i/o general port c [15:8] nsmwp i/o general port c [7] nsmwe i/o general port c [6] nsmre i/o general port c [5] nsmce i/o general port c [4] smcle i/o general port c [3] smale i/o general port c [2] nsmrb i/o general port c [1] nsmcd i/o general port c [0] ld[7:0] i/o general port d [24:17] lcden i/o general port d [16] lfp i/o general port d [15] lcp i/o general port d [14] lblen i/o general port d [13] lac i/o general port d [12] llp i/o general port d [11] scke[1] i/o general port d [10] scke[0] i/o general port d [9] nscs[1] i/o general port d [8] nscs[0] i/o general port d [7] nras i/o general port d [6] ncas i/o general port d [5] nswe i/o general port d [4] dqmu i/o general port d [3]
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 291 - dqml i/o general port d [2] nrcs[3] i/o general port d [1] nrcs[2] i/o general port d [0] pwm[1:0] i/o general port e [15:14] timer[3:0] i/o general port e [13:10] sda i/o general port e [9] scl i/o general port e [8] spiclk[1] i/o general port e [7] nssics[1] i/o general port e [6] ssitx[1] i/o general port e [5] ssirx[1] i/o general port e [4] ssiclk[0] i/o general port e [3] nssics[0] i/o general port e [2] ssitx[0] i/o general port e [1] ssirx[0] i/o general port e [0] refer to figure 2-1. 208 pin diagram.
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 292 - 9.14.2 registers address name width default description 0x8006.2000 adata 12 0x000 port a data register 0x8006.2004 adir 12 0xfff port a data direction register 0x8006.2008 aie 12 0x000 port a interrupt enable register 0x8006.200c astat 12 0x000 port a interrupt status register 0x8006.2010 aedge 12 0x000 port a edge interrupt register 0x8006.2014 aclr 12 0x000 port a interrupt clear register 0x8006.2018 apol 12 0x000 port a interrupt polarity register 0x8006.201c aen 12 0x000 port a enable register 0x8006.2020 bdata 28 0x00000000 port b data register 0x8006.2024 bdir 28 0x1fffffff port b data direction register 0x8006.2028 bie 28 0x00000000 port b interrupt enable register 0x8006.202c bstat 28 0x00000000 port b interrupt status register 0x8006.2030 bedge 28 0x00000000 port b edge interrupt register 0x8006.2034 bclr 28 0x00000000 port b interrupt clear register 0x8006.2038 bpol 28 0x00000000 port b interrupt polarity register 0x8006.203c ben 28 0x00000000 port b enable register 0x8006.2040 cdata 16 0x0000 port c data register 0x8006.2044 cadir 16 0xffff port c data direction register 0x8006.2048 cie 16 0x0000 port c interrupt enable register 0x8006.204c cstat 16 0x0000 port c interrupt status register 0x8006.2050 cedge 16 0x0000 port c edge interrupt register 0x8006.2054 cclr 16 0x0000 port c interrupt clear register 0x8006.2058 cpol 16 0x0000 port c interrupt polarity register 0x8006.205c cen 16 0x0000 port c enable register 0x8006.2060 ddata 25 0x0000000 port d data register 0x8006.2064 ddir 25 0x1ffffff port d data direction register 0x8006.2068 die 25 0x0000000 port d interrupt enable register 0x8006.206c dstat 25 0x0000000 port d interrupt status register 0x8006.2070 dedge 25 0x0000000 port d edge interrupt register 0x8006.2074 dclr 25 0x0000000 port d interrupt clear register 0x8006.2078 dpol 25 0x0000000 port d interrupt polarity register 0x8006.207c den 25 0x0000000 port d enable register 0x8006.2080 edata 16 0x00000 port e data register 0x8006.2084 edir 16 0x1ffff port e data direction register 0x8006.2088 eie 16 0x00000 port e interrupt enable register 0x8006.208c estat 16 0x00000 port e interrupt status register 0x8006.2090 eedge 16 0x00000 port e edge interrupt register 0x8006.2094 eclr 16 0x00000 port e interrupt clear register 0x8006.2098 epol 16 0x00000 port e interrupt polarity register 0x8006.209c een 16 0x00000 port e enable register 0x8006.20a4 adebe 12 0x000 port a de-bounce enable register 0x8006.20a8 bdebe 1 0x0 port b de-bounce enable register
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 293 - 9.14.2.1 port a data register (adata) 0x8006.2000 11 10 ... 1 0 data, dir, inten, stat, edge, clr, pol, enable [7:0] bits type function 12 r/w port a output data values written to this register will be output on port a pins if the corresponding bits of port a direction register are zeros (port pin is configured as output). values read from the address of this register reflect the external state of port a not the value written to this register. all bits are cleared by a system reset. when the port pin is configured as input, this input can be an interrupt source with appropriate register setting. when dir[n] bit in adir register is 0, 0 = drives port a[n] pin low. (default) 1 = drives port a[n] pin high. when dir[n] bit in adir register is 1, 0 = the read value on port a[n] is ?0?. (default) 1 = the read value on port a[n] is ?1?. 9.14.2.2 port a direction register (adir) 0x8006.2004 11 10 ... 1 0 dir [7:0] bits type function 12 r/w port a direction bits set in this register will select the corresponding pin of port a to configured as an input. all bits are set by a system reset. 0 = port a[n] is configured as an output. 1 = port a[n] is configured as an input. (default)
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 294 - 9.14.2.3 port a interrupt enable register (aie) 0x8006.2008 11 10 ... 1 0 inten [11:0] bits type function 12 r/w port a interrupt enable bits set in this register make the corresponding pins of port a to become an external interrupt source. all bits are cleared by a system reset. 0 = disable interrupt. (default) 1 = enable interrupt 9.14.2.4 port a interrupt status register (astat) 0x8006.200c 11 10 ... 1 0 stat [11:0] bits type function 12 r port a interrupt status all pio signals can be used as interrupt sources according to the settings. each port has the following registers and interrupt signals to interrupt controller. the interrupt controller unit of HMS30C7210 receives active high level interrupt sources only. but gpio block can receive not only active high or active low level, but also rising or falling edge signals. then interprets and sends interrupt request to the interrupt controller. all bits can be controlled separately. values in this read-only register represents that the interrupt requests are pending on corresponding pins. all bits are cleared by a system reset. 0 = interrupt is cleared or no interrupt is requested. (default) 1 = interrupt pending.
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 295 - 9.14.2.5 port a edge interrupt register (aedge) 0x8006.2010 11 10 ... 1 0 edge [11:0] bits type function 12 r/w port a interrupts are edge triggered all pins of port a can be an external interrupt source. and the external interrupts can be triggered by detecting an edge or a level. bits set in this register makes the corresponding pins of port a to be edge triggered interrupt source. all bits are cleared by a system reset. 0 = external interrupt is triggered by level. (default) 1 = external interrupt is triggered by edge. 9.14.2.6 port a interrupt clear register (aclr) 0x8006.2014 11 10 ... 1 0 clr [11:0] bits type function 12 w port a interrupt clear if a edge triggered interrupt is used, the status register (astat) and interrupt pending are cleared by writing ?1? in the corresponding bit position of this register. all bits are automatically cleared after written. this register is write only. 0 = no action is done. (default) 1 = clear edge triggered interrupt request and interrupt status register (astat). 9.14.2.7 port a interrupt polarity register (apol) 0x8006.2018 11 10 ... 1 0 pol [11:0] bits type function 12 r/w port a interrupt polarity if level triggered interrupts are used, bits set in this register activate the interrupts when the level of corresponding pins of port a is low. if edge triggered interrupts are used, bits set in this register activate the interrupts when the corresponding pins of port a make an falling edge. all bits are cleared by a system reset. when interrupt is level sensitive (edge[n] in aedge register is 0), 0 = external interrupt is triggered by a high level. (default) 1 = external interrupt is triggered by a low level. when interrupt is edge triggered (edge[n] in aedge register is 1), 0 = external interrupt is triggered by a rising edge. (default) 1 = external interrupt is triggered by a falling edge.
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 296 - 9.14.2.8 port a enable register (aen) 0x8006.201c 11 10 ... 1 0 enable [11:0] bits type function 11 r/w port a[11] enable setting this bit makes the pin kscano[5] to be used as general digital i/o pin. 0 = port a[11] is used as kscano[5]. (default) 1 = port a[11] is used as general i/o pin. 10 r/w port a[10] enable 0 = port a[10] is used as kscano[4]. (default) 1 = port a[10] is used as general i/o pin. 9 r/w port a[9] enable 0 = port a[9] is used as kscano[3]. (default) 1 = port a[9] is used as general i/o pin. 8 r/w port a[8] enable 0 = port a[8] is used as kscano[2]. (default) 1 = port a[8] is used as general i/o pin. 7 r/w port a[7] enable 0 = port a[7] is used as kscano[1]. (default) 1 = port a[7] is used as general i/o pin. 6 r/w port a[6] enable 0 = port a[6] is used as kscano[0]. (default) 1 = port a[6] is used as general i/o pin. 5 r/w port a[5] enable 0 = port a[5] is used as kscani[5]. (default) 1 = port a[5] is used as general i/o pin. 4 r/w port a[4] enable 0 = port a[4] is used as kscani[4]. (default) 1 = port a[4] is used as general i/o pin. 3 r/w port a[3] enable 0 = port a[3] is used as kscani[3]. (default) 1 = port a[3] is used as general i/o pin. 2 r/w port a[2] enable 0 = port a[2] is used as kscani[2]. (default) 1 = port a[2] is used as general i/o pin. 1 r/w port a[1] enable 0 = port a[1] is used as kscani[1]. (default) 1 = port a[1] is used as general i/o pin. 0 r/w port a[0] enable 0 = port a[0] is used as kscani[0]. (default) 1 = port a[0] is used as general i/o pin.
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 297 - 9.14.2.9 port b data register (bdata) 0x8006.2020 27 26 ... 1 0 data, dir, inten, stat, edge, clr, pol, enable [27:0] 9.14.2.10 port b direction register (bdir) 0x8006.2024 27 26 ... 1 0 dir [27:0] 9.14.2.11 port b interrupt enable register (bie) 0x8006.2028 27 26 ... 1 0 inten [27:0] 9.14.2.12 port b interrupt status register (bstat) 0x8006.202c 27 26 ... 1 0 stat [27:0] 9.14.2.13 port b edge interrupt register (bedge) 0x8006.2030 27 26 ... 1 0 edge [27:0] 9.14.2.14 port b interrupt clear register (bclr) 0x8006.2034 27 26 ... 1 0 clr [27:0] 9.14.2.15 port b interrupt polarity register (bpol) 0x8006.2038 27 26 ... 1 0 pol [27:0] 9.14.2.16 port b enable register (ben) 0x8006.203c 27 26 ... 1 0 enable [27:0]
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 298 - bits type function 27 r/w port b[27] enable setting this bit makes the pin uart5tx to be used as general digital i/o pin. 0 = port b[27] is used as uart5tx. (default) 1 = port b[27] is used as general i/o pin. 26 r/w port b[26] enable 0 = port b[26] is used as uart5rx. (default) 1 = port b[26] is used as general i/o pin. 25 r/w port b[25] enable 0 = port b[25] is used as nudcd. (default) 1 = port b[25] is used as general i/o pin. 24 r/w port b[24] enable 0 = port b[24] is used as nudsr. (default) 1 = port b[24] is used as general i/o pin. 23 r/w port b[23] enable 0 = port b[23] is used as nurts. (default) 1 = port b[23] is used as general i/o pin. 22 r/w port b[22] enable 0 = port b[22] is used as nucts. (default) 1 = port b[22] is used as general i/o pin. 21 r/w port b[21] enable 0 = port b[21] is used as nudtr. (default) 1 = port b[21] is used as general i/o pin. 20 r/w port b[20] enable 0 = port b[20] is used as nuring. (default) 1 = port b[20] is used as general i/o pin. 19 r/w port b[19] enable 0 = port b[19] is used as touchyn. (default) 1 = port b[19] is used as general i/o pin. 18 r/w port b[18] enable 0 = port b[18] is used as touchxn. (default) 1 = port b[18] is used as general i/o pin. 17 r/w port b[17] enable 0 = port b[17] is used as touchyp. (default) 1 = port b[17] is used as general i/o pin. 16 r/w port b[16] enable 0 = port b[16] is used as touchxp. (default) 1 = port b[16] is used as general i/o pin. 15 r/w port b[15] enable 0 = port b[15] is used as hotsync input to pmu unit. (default) 1 = port b[15] is used as general i/o pin. 14 r/w port b[14] enable 0 = port b[14] is used as todeepsleep input to pmu unit. (default) 1 = port b[14] is used as general i/o pin 13 r/w port b[13] enable 0 = port b[13] is used as irdatx. (default) 1 = port b[13] is used as general i/o pin. 12 r/w port b[12] enable 0 = port b[12] is used as irdarx. (default) 1 = port b[12] is used as general i/o pin. 11 r/w port b[11] enable 0 = port b[11 is used as uart3tx. (default) 1 = port b[11] is used as general i/o pin. 10 r/w port b[10] enable 0 = port b[10] is used as uart3rx. (default) 1 = port b[10] is used as general i/o pin. 9 r/w port b[9] enable 0 = port b[9] is used as uart2tx. (default) 1 = port b[9] is used as general i/o pin. 8 r/w port b[8] enable 0 = port b[8] is used as uart2rx. (default) 1 = port b[8] is used as general i/o pin.
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 299 - 7 r/w port b[7] enable 0 = port b[7] is used as scpres[1]. (default) 1 = port b[7] is used as general i/o pin. 6 r/w port b[6] enable 0 = port b[6] is used as scclk[1]. (default) 1 = port b[6] is used as general i/o pin. 5 r/w port b[5] enable 0 = port b[5] is used as scio[1]. (default) 1 = port b[5] is used as general i/o pin. 4 r/w port b[4] enable 0 = port b[4] is used as scrst[1]. (default) 1 = port b[4] is used as general i/o pin. 3 r/w port b[3] enable 0 = port b[3] is used as scpres[0]. (default) 1 = port b[3] is used as general i/o pin. 2 r/w port b[2] enable 0 = port b[2] is used as scclk[0]. (default) 1 = port b[2] is used as general i/o pin. 1 r/w port b[1] enable 0 = port b[1] is used as scio[0]. (default) 1 = port b[1] is used as general i/o pin. 0 r/w port b[0] enable 0 = port b[0] is used as scrst[0]. (default) 1 = port b[0] is used as general i/o pin.
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 300 - 9.14.2.17 port c data register (cdata) 0x8006.2040 15 14 ... 1 0 data, dir, inten, stat, edge, clr, pol, enable[15:0] 9.14.2.18 port c direction register (cdir) 0x8006.2044 15 14 ... 1 0 dir [15:0] 9.14.2.19 port c interrupt enable register (cie) 0x8006.2048 15 14 ... 1 0 inten [15:0] 9.14.2.20 port c interrupt status register (cstat) 0x8006.204c 15 14 ... 1 0 stat [15:0] 9.14.2.21 port c edge interrupt register (cedge) 0x8006.2050 15 14 ... 1 0 edge [15:0] 9.14.2.22 port c interrupt clear register (cclr) 0x8006.2054 15 14 ... 1 0 clr [15:0] 9.14.2.23 port c interrupt polarity register (cpol) 0x8006.2058 15 14 ... 1 0 pol [15:0] 9.14.2.24 port c enable register (cen) 0x8006.205c 15 14 ... 1 0 enable [15:0]
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 301 - bits type function 15 r/w port c[15] enable setting this bit makes the pin smd[7] to be used as general digital i/o pin. 0 = port c[15] is used as smd[7]. (default) 1 = port c[15] is used as general i/o pin. 14 r/w port c[14] enable 0 = port c[14] is used as smd[6]. (default) 1 = port c[14] is used as general i/o pin 13 r/w port c[13] enable 0 = port c[13] is used as smd[5]. (default) 1 = port c[13] is used as general i/o pin. 12 r/w port c[12] enable 0 = port c[12] is used as smd[4]. (default) 1 = port c[12] is used as general i/o pin. 11 r/w port c[11] enable 0 = port c[11 is used as smd[3]. (default) 1 = port c[11] is used as general i/o pin. 10 r/w port c[10] enable 0 = port c[10] is used as smd[2]. (default) 1 = port c[10] is used as general i/o pin. 9 r/w port c[9] enable 0 = port c[9] is used as smd[1]. (default) 1 = port c[9] is used as general i/o pin. 8 r/w port c[8] enable 0 = port c[8] is used as smd[0]. (default) 1 = port c[8] is used as general i/o pin. 7 r/w port c[7] enable 0 = port c[7] is used as nsmwp. (default) 1 = port c[7] is used as general i/o pin. 6 r/w port c[6] enable 0 = port c[6] is used as nsmwe. (default) 1 = port c[6] is used as general i/o pin. 5 r/w port c[5] enable 0 = port c[5] is used as nsmre. (default) 1 = port c[5] is used as general i/o pin. 4 r/w port c[4] enable 0 = port c[4] is used as nsmce. (default) 1 = port c[4] is used as general i/o pin. 3 r/w port c[3] enable 0 = port c[3] is used as smcle. (default) 1 = port c[3] is used as general i/o pin. 2 r/w port c[2] enable 0 = port c[2] is used as smale. (default) 1 = port c[2] is used as general i/o pin. 1 r/w port c[1] enable 0 = port c[1] is used as nsmrb. (default) 1 = port c[1] is used as general i/o pin. 0 r/w port c[0] enable 0 = port c[0] is used as nsmcd. (default) 1 = port c[0] is used as general i/o pin.
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 302 - 9.14.2.25 port d data register (ddata) 0x8006.2060 24 23 ... 1 0 data, dir, mask, stat, edge, clr, pol, enable[24:0] 9.14.2.26 port d direction register (ddir) 0x8006.2064 24 23 ... 1 0 dir [24:0] 9.14.2.27 port d interrupt enable register (die) 0x8006.2068 24 23 ... 1 0 inten [24:0] 9.14.2.28 port d interrupt status register (dstat) 0x8006.206c 24 23 ... 1 0 stat [24:0] 9.14.2.29 port d edge interrupt register (dedge) 0x8006.2070 24 23 ... 1 0 edge [24:0] 9.14.2.30 port d interrupt clear register (dclr) 0x8006.2074 24 23 ... 1 0 clr [24:0] 9.14.2.31 port d interrupt polarity register (dpol) 0x8006.2078 24 23 ... 1 0 pol [24:0] 9.14.2.32 port d enable register (den) 0x8006.207c 24 23 ... 1 0 enable [24:0]
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 303 - bits type function 24 r/w port d[24] enable setting this bit makes the pin ld[7] to be used as general digital i/o pin. 0 = port d[24] is used as ld[7]. (default) 1 = port d[24] is used as general i/o pin. 23 r/w port d[23] enable 0 = port d[23] is used as ld[6]. (default) 1 = port d[23] is used as general i/o pin. 22 r/w port d[22] enable 0 = port d[22] is used as ld[5]. (default) 1 = port d[22] is used as general i/o pin. 21 r/w port d[21] enable 0 = port d[21] is used as ld[4]. (default) 1 = port d[21] is used as general i/o pin. 20 r/w port d[20] enable 0 = port d[20] is used as ld[3]. (default) 1 = port d[20] is used as general i/o pin. 19 r/w port d[19] enable 0 = port d[19] is used as ld[2]. (default) 1 = port d[19] is used as general i/o pin. 18 r/w port d[18] enable 0 = port d[18] is used as ld[1]. (default) 1 = port d[18] is used as general i/o pin. 17 r/w port d[17] enable 0 = port d[17] is used as ld[0]. (default) 1 = port d[17] is used as general i/o pin. 16 r/w port d[16] enable 0 = port d[16] is used as lcden. (default) 1 = port d[16] is used as general i/o pin. 15 r/w port d[15] enable 0 = port d[15] is used as lfp. (default) 1 = port d[15] is used as general i/o pin. 14 r/w port d[14] enable 0 = port d[14] is used as lcp. (default) 1 = port d[14] is used as general i/o pin 13 r/w port d[13] enable 0 = port d[13] is used as lblen. (default) 1 = port d[13] is used as general i/o pin. 12 r/w port d[12] enable 0 = port d[12] is used as lac. (default) 1 = port d[12] is used as general i/o pin. 11 r/w port d[11] enable 0 = port d[11 is used as llp. (default) 1 = port d[11] is used as general i/o pin. 10 r/w port d[10] enable 0 = port d[10] is used as scke[1]. (default) 1 = port d[10] is used as general i/o pin. 9 r/w port d[9] enable 0 = port d[9] is used as scke[0]. (default) 1 = port d[9] is used as general i/o pin. 8 r/w port d[8] enable 0 = port d[8] is used as nscs[1]. (default) 1 = port d[8] is used as general i/o pin. 7 r/w port d[7] enable 0 = port d[7] is used as nscs[0]. (default) 1 = port d[7] is used as general i/o pin. 6 r/w port d[6] enable 0 = port d[6] is used as nras. (default) 1 = port d[6] is used as general i/o pin. 5 r/w port d[5] enable 0 = port d[5] is used as ncas. (default) 1 = port d[5] is used as general i/o pin.
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 304 - 4 r/w port d[4] enable 0 = port d[4] is used as swe. (default) 1 = port d[4] is used as general i/o pin. 3 r/w port d[3] enable 0 = port d[3] is used as dqmu. (default) 1 = port d[3] is used as general i/o pin. 2 r/w port d[2] enable 0 = port d[2] is used as dqml. (default) 1 = port d[2] is used as general i/o pin. 1 r/w port d[1] enable 0 = port d[1] is used as nrcs[3]. (default) 1 = port d[1] is used as general i/o pin. 0 r/w port d[0] enable 0 = port d[0] is used as nrcs[2]. (default) 1 = port d[0] is used as general i/o pin.
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 305 - 9.14.2.33 port e data register (edata) 0x8006.2080 15 14 ... 1 0 data, dir, inten, stat, edge, clr, pol, enable [15:0] 9.14.2.34 port e direction register (edir) 0x8006.2084 15 14 ... 1 0 dir [15:0] 9.14.2.35 port e interrupt enable register (eie) 0x8006.2088 15 14 ... 1 0 inten [15:0] 9.14.2.36 port e interrupt status register (estat) 0x8006.208c 15 14 ... 1 0 stat [15:0] 9.14.2.37 port e edge interrupt register (eedge) 0x8006.2090 15 14 ... 1 0 edge [15:0] 9.14.2.38 port e interrupt clear register (eclr) 0x8006.2094 15 14 ... 1 0 clr [15:0] 9.14.2.39 port e interrupt polarity register (epol) 0x8006.2098 15 14 ... 1 0 pol [15:0] 9.14.2.40 port e enable register (een) 0x8006 209c 15 14 ... 1 0 enable [15:0]
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 306 - bits type function 15 r/w port e[15] enable setting this bit makes the pin pwm[1] to be used as general digital i/o pin. 0 = port e[15] is used as pwm[1]. (default) 1 = port e[15] is used as general i/o pin. 14 r/w port e[14] enable 0 = port e[14] is used as pwm[0]. (default) 1 = port e[14] is used as general i/o pin 13 r/w port e[13] enable 0 = port e[13] is used as tiemr[3]. (default) 1 = port e[13] is used as general i/o pin. 12 r/w port e[12] enable 0 = port e[12] is used as timer[2]. (default) 1 = port e[12] is used as general i/o pin. 11 r/w port e[11] enable 0 = port e[11 is used as timer[1]. (default) 1 = port e[11] is used as general i/o pin. 10 r/w port e[10] enable 0 = port e[10] is used as timer[0]. (default) 1 = port e[10] is used as general i/o pin. 9 r/w port e[9] enable 0 = port e[9] is used as sda. (default) 1 = port e[9] is used as general i/o pin. 8 r/w port e[8] enable 0 = port e[8] is used as scl. (default) 1 = port e[8] is used as general i/o pin. 7 r/w port e[7] enable 0 = port e[7] is used as spiclk[1]. (default) 1 = port e[7] is used as general i/o pin. 6 r/w port e[6] enable 0 = port e[6] is used as nspics[1]. (default) 1 = port e[6] is used as general i/o pin. 5 r/w port e[5] enable 0 = port e[5] is used as spitx[1]. (default) 1 = port e[5] is used as general i/o pin. 4 r/w port e[4] enable 0 = port e[4] is used as spirx[1]. (default) 1 = port e[4] is used as general i/o pin. 3 r/w port e[3] enable 0 = port e[3] is used as spiclk[0]. (default) 1 = port e[3] is used as general i/o pin. 2 r/w port e[2] enable 0 = port e[2] is used as nspics[0]. (default) 1 = port e[2] is used as general i/o pin. 1 r/w port e[1] enable 0 = port e[1] is used as spitx[0]. (default) 1 = port e[1] is used as general i/o pin. 0 r/w port e[0] enable 0 = port e[0] is used as spirx[0]. (default) 1 = port e[0] is used as general i/o pin.
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 307 - 9.14.2.41 port a de-bounce enable register (adebe) 0x8006 20a4 11 10 ... 1 0 adbnc[11:0] bits type function 11 r/w port a[11] input de-bounce enable the input signal of port a[11] can be de-bounced by setting this bit to remove mechanical jitter. if this bit is cleared, input signal of port a[11] reflects the status of pin kscano[5] immediately. 0 = port a[11] input is used directly. (default) 1 = port a[11] input is used after de-bouncing. 10 r/w port a[10] input de-bounce enable 0 = port a[10] input is used directly. (default) 1 = port a[10] input is used after de-bouncing. 9 r/w port a[9] input de-bounce enable 0 = port a[9] input is used directly. (default) 1 = port a[9] input is used after de-bouncing. 8 r/w port a[8] input de-bounce enable 0 = port a[8] input is used directly. (default) 1 = port a[8] input is used after de-bouncing 7 r/w port a[7] input de-bounce enable 0 = port a[7] input is used directly. (default) 1 = port a[7] input is used after de-bouncing 6 r/w port a[6] input de-bounce enable 0 = port a[6] input is used directly. (default) 1 = port a[6] input is used after de-bouncing. 5 r/w port a[5] input de-bounce enable 0 = port a[5] input is used directly. (default) 1 = port a[5] input is used after de-bouncing. 4 r/w port a[4] input de-bounce enable 0 = port a[4] input is used directly. (default) 1 = port a[4] input is used after de-bouncing. 3 r/w port a[3] input de-bounce enable 0 = port a[3] input is used directly. (default) 1 = port a[3] input is used after de-bouncing. 2 r/w port a[2] input de-bounce enable 0 = port a[2] input is used directly. (default) 1 = port a[2] input is used after de-bouncing. 1 r/w port a[1] input de-bounce enable 0 = port a[1] input is used directly. (default) 1 = port a[1] input is used after de-bouncing. 0 r/w port a[0] input de-bounce enable 0 = port a[0] input is used directly. (default) 1 = port a[0] input is used after de-bouncing.
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 308 - 9.14.2.42 port b de-bounce enable register (bdebe) 0x8006.20a8 0 bdbnc14 bits type function 0 r/w port b[14] input de-bounce enable the input signal of port b[14] can be de-bounced by setting this bit to remove mechanical jitter. if this bit is cleared, input signal of port b[14] reflects the status of pin gpiob14 immediately. 0 = port b[14] input is used directly. (default) 1 = port b[14] input is used after de-bouncing.
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 309 - 9.14.3 operations throughout the operation description of each port, port a is used as an example port. all is same to other ports. 9.14.3.1 configuring the pin the dir[n] bit in the adir register selects the direction of this pin. if dir[n] is written logic one, port a[n] is configured as an input pin. if dir[n] is written logic zero, port a[n] is configured as an output pin. note that port a[n] can be used as an input or output pin only when enable[n] bit in the aen register is written logic one. otherwise, port a[n] is used as an primary function pin. 9.14.3.2 writing the pin value values written to adata register will be output on port a pins if the corresponding bits of port a direction register are zeros. the pin of port a[n] is driven high when the data[n] bit in adata register is written logic one. and the pin of port a[n] is driven low when the data[n] is written logic zero. 9.14.3.3 reading the pin value independent of the setting of data direction bit dir[n], the port pin can be read through the adata register bit. in that case, enable[n] bit in the aen register must be written logic one to read the pin value. if enable[n] bit is written logic zero, the pin value will be read as zero.
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 310 - 9.14.3.4 alternate port functions all port pins have alternate functions in addition to being general digital i/os. the alternate function can be selected by clearing enable[n] bit in each port enable register. if enable[n] bit in the aen register is written logic one, port a[n] is configured as an general digital i/o and if enable[n] is written zero, port a[n] is used by alternate function block. for example if aen[11:0] is written value 0xf00, port a[7:0] are used for keyboard function, and port a[11:8] are used as general i/os. pin fnoe dir[n] enable[n] fdataout data[n] enable[n] port input (read data) extin[n] 1 0 1 0 fdatain enable[n] extin[n] : pin value fdatain : in p ut value to alternate function fdatain : block fdataout : output value from alternate fdataout : function block fnoe : output enable signal from alternate fnoe : function block figure 9-68. alternate port functions
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 311 - 9.14.3.5 external interrupt request gpio has 7 interrupt sources. each port can be configured as 1 interrupt source except port b. that is, if any pin of port a makes an interrupt condition, an interrupt is requested form port a. in order to use a port a as an interrupt source, specify edge[n] bits in aedge register and pol[n] bits in apol register according to interrupt type. and then set the inten[n] bits in aie register to enable interrupt request. the usage of port c, d and e is same as port a. unlike other ports, port b has 3 interrupt sources. ? the first interrupt source comes from port b[27:16] or port b[13:0], and these port pins are used as normal external interrupt sources like other port pins. ? the second interrupt source is port b[15] (gpiob[15]). gpiob[15] is used to detect hotsync. when pmu is in deepsleep or sleep modes, the interrupt of port b[15] makes the pmu wake-up. ? and the third interrupt source is port b[14] (gpiob[14]). gpiob[14] is required to make the operating mode of pmu unit go to deepsleep mode. changing the operation mode of pmu unit is software?s responsibility. that is, when gpiob[14] triggers an interrupt, the interrupt handler forces the pmu to enter deepsleep mode. inten[n] edge detector 0 1 extin[n] : pin value interrupt : interrupt request from port a[n] extin pol[n] q d cp edge[n] r clr[n] interrupt level detector figure 9-69. interrupt request
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 312 - there are 4 cases to trigger an interrupt, and the sequence to trigger an interrupt is shown below. port a is used to be an interrupt source. note that interrupt clear methods are different according to the triggering condition. a high level of port pin ? decide port pins to be interrupt sources. ? write zeros to the selected bits in apol register. ? write zeros to the selected bits in aedge register. ? enable interrupts by writing ones to the selected bits in aie register. ? if interrupt is requested, the external port pin must be changed to low level to clear interrupt request. a low level of port pin ? decide port pins to be interrupt sources. ? write ones to the selected bits in apol register. ? write zeros to the selected bits in aedge register. ? enable interrupts by writing ones to the selected bits in aie register. ? if interrupt is requested, the external port pin must be changed to high level to clear interrupt request. a rising edge of port pin ? decide port pins to be interrupt sources. ? write zeros to the selected bits in apol register. ? write ones to the selected bits in aedge register. ? enable interrupts by writing ones to the selected bits in aie register. ? if interrupt is requested, the handler writes one to aclr register (corresponding bit position). a falling edge of port pin ? decide port pins to be interrupt sources. ? write ones to the selected bits in apol register. ? write ones to the selected bits in aedge register. ? enable interrupts by writing ones to the selected bits in aie register. ? if interrupt is requested, the handler writes one to aclr register (corresponding bit position). interrupt name configurable bits gpioaint port a[11:0] gpiobint port b[27:0] gpiocint port c[15:0] gpiodint port d[24:0] gpioeint port e[15:0] gpiob14int port b[14], deep sleep interrupt gpiob15int port b[15], hotsync interrupt table 9-22. interrupt sources of i/os (to interrupt controller unit)
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 313 - 9.14.3.6 de-bouncing port a and port b[14] all pins of port a and gpiob[14] can be de-bounced before being used as input signals. if adbnc[n] bit in adebe register is written logic one, the input signal of port a[n] is de-bounced by a slow clock, and the de-bounced signal is used in alternate function block or interrupt source of port a[n]. also, the read value of port a[n] is de- bounced signal. in port b, only gpiob[14] can be de-bounced. extin[n] de-bounce logic in pmu unit 0 1 q d cp r de-bounce clear interrupt level detector adbnc[n] alternate function block pin port out enable[n] port output[n] debncout[n] de-bounce clock bi-dir external to HMS30C7210 figure 9-70. de-bouncing of port a
amba peripherals (gpio) magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 314 - 9.14.4 gpio rise and fall time this sections describes the rise and fall time of each pad pin. the pad library cells used in HMS30C7210 are symbolized as pc3b01, pc3b03 and pt3b03. pc3b01 and pc3b03 cells are three state cmos input/output pads with ac drive capability of 1x and 3x. pt3b03 cells are three state ttl input/output pads with dc drive capability of 8ma. the following 2 figures depicts pad organization and waveform respectively. and these figures are used to explain timing symbols. the symbol tcmos or tttl mean the propagation delay from i to pad of cmos or ttl pad and toen means the propagation delay from oen to pad of each pad cell. pad cin i oen figure 9-71. pad organization i oen pad cin toen tttl or tcmos figure 9-72. timing diagram of bi-directional pad (cmos or ttl) the propagation delay listed in the following table is rounded off to three decimal places. 50pf 100pf 150pf port name rise(ns) fall(ns) rise(ns) fall(ns) rise(ns) fall(ns) tcmos 5.60 4.94 9.80 8.29 14.01 11.64 pc3b01 toen 5.92 4.25 10.10 7.63 14.29 11.02 tcmos 3.60 3.74 5.71 5.39 7.82 7.04 pc3b03 toen 3.84 2.53 5.93 4.21 8.02 5.90 tttl 2.71 2.74 4.17 3.87 5.63 5.00 pt3b03 toen 3.28 1.96 4.72 3.12 6.15 4.27 table 9-23. propagation delays (ns) for sample pad loads
debug and test interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 315 - 10 debug and test interface 10.1 overview the HMS30C7210 has built-in features that enable debug and test in a number of different contexts. firstly, there are circuit structures to help with software development. secondly, the device contains boundary scan cells for circuit board test. finally, the device contains some special test modes that enable the generation production patterns for the device itself. 10.2 software development debug and test interface the arm720t processors incorporated inside HMS30C7210 contain hardware extensions for advanced debugging features. these are intended to ease user development and debugging of application software, operating systems, and the hardware itself. full details of the debug interfaces and their programming can be found in arm720t data sheet (arm ddi-0087). the multiice product enables the arm720t macrocells to be debugged in one environment. refer to guide to multiice (arm dui-0048).
debug and test interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 316 - 10.3 test access port and boundary-scan HMS30C7210 contains full boundary scan on its inputs and outputs to help with circuit board test. this supports both intest and extest, allowing patterns to be applied serially to the hms30c7202 when fixed in a board and for full circuit board connection respectively. the boundary-scan interface conforms to the ieee std. 1149.1- 1990, standard test access port and boundary-scan architecture. (please refer to this standard for an explanation of the terms used in this section and for a description of the tap controller states.) the boundary-scan interface provides a means of testing the core of the device when it is fitted to a circuit board, and a means of driving and sampling all the external pins of the device irrespective of the core state. this latter function permits testing of both the device's electrical connections to the circuit board, and (in conjunction with other devices on the circuit board having a similar interface) testing the integrity of the circuit board connections between devices. the interface intercepts all external connections within the device, and each such ?cell? is then connected together to form a serial register (the boundary scan register). the whole interface is controlled via 5 dedicated pins: tdi , tms , tck , ntrst and tdo . figure 11-1: test access port (tap) controller state transitions shows the state transitions that occur in the tap controller. figure 10-1. test access port(tap) controller state transitions
debug and test interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 317 - 10.3.1 reset the boundary-scan interface includes a state-machine controller (the tap controller). a pulldown resistor is included in the ntrst pad which holds the tap controller state machine in a safe state after power up. in order to use the boundary scan interface, ntrst should be driven high to take the tap state machine out of reset. the action of reset (either a pulse or a dc level) is as follows: ? system mode is selected (i.e. the boundary scan chain does not intercept any of the signals passing between the pads and the core). ? idcode mode is selected. if tck is pulsed, the contents of the id register will be clocked out of tdo . note the tap controller inside HMS30C7210 contains a scan chip register which is reset to the value b0011 thus selecting the boundary scan chain. if this register is programmed to any value other than b0011, then it must be reprogrammed with b0011 or a reset applied before boundary scan operation can be attempted.
debug and test interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 318 - 10.3.2 pull-up register the ieee 1149.1 standard requires pullup resistors in the input pins. however, to ensure safe operation an internal pulldown is present in the ntrst pin and therefore will have to be driven high when using this interface. pin name internal resistor tclk pull-up ntrst pull-down tms pull-up tdi pull-up 10.3.3 instruction register the instruction register is 4 bits in length. there is no parity bit. the fixed value loaded into the instruction register during the capture-ir controller state is: 0001.
debug and test interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 319 - 10.3.4 public instructions the following public instructions are supported: instruction binary code extest 0000 sample/preload 0011 clamp 0101 highz 0111 clampz 1001 intest 1100 idcode 1110 bypass 1111 in the descriptions that follow, tdi and tms are sampled on the rising edge of tck and all output transitions on tdo occur as a result of the falling edge of tc k.
debug and test interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 320 - extest (0000) the bs (boundary-scan) register is placed in test mode by the extest instruction.the extest instruction connects the bs register between tdi and tdo .when the instruction register is loaded with the extest instruction, all the boundary-scan cells are placed in their test mode of operation. in the capture-dr state, inputs from the system pins and outputs from the boundary-scan output cells to the system pins are captured by the boundary-scan cells. in the shift-dr state, the previously captured test data is shifted out of the bs register via the tdo pin, whilst new test data is shifted in via the tdi pin to the bs register parallel input latch. in the update -dr state, the new test data is transferred into the bs register parallel output latch. note that this data is applied immediately to the system logic and system pins. the first extest vector should be clocked into the boundary-scan register, using the sample/preload instruction, prior to selecting extest to ensure that known data is applied to the system logic. sample/preload (0011) the bs (boundary-scan) register is placed in normal (system) mode by the sample/preload instruction. the sample/preload instruction connects the bs register between tdi and tdo . when the instruction register is loaded with the sample/preload instruction, all the boundary-scan cells are placed in their normal system mode of operation. in the capture-dr state, a snapshot of the signals at the boundary-scan cells is taken on the rising edge of tck . normal system operation is unaffected. in the shift-dr state, the sampled test data is shifted out of the bs register via the tdo pin, whilst new data is shifted in via the tdi pin to preload the bs register parallel input latch. in the update-dr state, the preloaded data is transferred into the bs register parallel output latch. note that this data is not applied to the system logic or system pins while the sample/preload instruction is active. this instruction should be used to preload the boundary-scan register with known data prior to selecting the intest or extest instructions. clamp (0101) the clamp instruction connects a 1 bit shift register (the bypass register) between tdi and tdo . when the clamp instruction is loaded into the instruction register, the state of all output signals is defined by the values previously loaded into the boundary-scan register. a guarding pattern should be pre-loaded into the boundary- scan register using the sample/preload instruction prior to selecting the clamp instruction. in the capture-dr state, a logic 0 is captured by the bypass register. in the shift-dr state, test data is shifted into the bypass register via tdi and out via tdo after a delay of one tck cycle. note that the first bit shifted out will be a zero. the bypass register is not affected in the update-dr state.
debug and test interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 321 - highz (0111) the highz instruction connects a 1 bit shift register (the bypass register) between tdi and tdo . when the highz instruction is loaded into the instruction register, all outputs are placed in an inactive drive state. in the capture-dr state, a logic 0 is captured by the bypass register. in the shift-dr state, test data is shifted into the bypass register via tdi and out via tdo after a delay of one tck cycle. note that the first bit shifted out will be a zero. the bypass register is not affected in the update- dr state. clampz (1001) the clampz instruction connects a 1 bit shift register (the bypass register) between tdi and tdo . when the clampz instruction is loaded into the instruction register, all outputs are placed in an inactive drive state, but the data supplied to the disabled output drivers is derived from the boundary-scan cells. the purpose of this instruction is to ensure, during production testing, that each output driver can be disabled when its data input is either a 0 or a 1. a guarding pattern (specified for this device at the end of this section) should be pre-loaded into the boundary-scan register using the sample/preload instruction prior to selecting the clampz instruction. in the capture-dr state, a logic 0 is captured by the bypass register. in the shift-dr state, test data is shifted into the bypass register via tdi and out via tdo after a delay of one tck cycle. note that the first bit shifted out will be a zero. the bypass register is not affected in the update-dr state. intest (1100) the bs (boundary-scan) register is placed in test mode by the intest instruction. the intest instruction connects the bs register between tdi and td o. when the instruction register is loaded with the intest instruction, all the boundary-scan cells are placed in their test mode of operation. in the capture-dr state, the complement of the data supplied to the core logic from input boundary-scan cells is captured, while the true value of the data that is output from the core logic to output boundary- scan cells is captured. note that capture-dr captures the complemented value of the input cells for testability reasons. in the shift-dr state, the previously captured test data is shifted out of the bs register via the tdo pin, whilst new test data is shifted in via the tdi pin to the bs register parallel input latch. in the update-dr state, the new test data is transferred into the bs register parallel output latch. note that this data is applied immediately to the system logic and system pins. the first intest vector should be clocked into the boundary-scan register, using the sample/preload instruction, prior to selecting intest to ensure that known data is applied to the system logic. single-step operation is possible using the intest instruction.
debug and test interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 322 - idcode (1110) the idcode instruction connects the device identification register (or id register) between tdi and td o. the id register is a 32-bit register that allows the manufacturer, part number and version of a component to be determined through the tap. the idcode returned will be that for the arm720t core. when the instruction register is loaded with the idcode instruction, all the boundary-scan cells are placed in their normal (system) mode of operation. in the capture-dr state, the device identification code (specified at the end of this section) is captured by the id register. in the shift-dr state, the previously captured device identification code is shifted out of the id register via the tdo pin, whilst data is shifted in via the tdi pin into the id register. in the update-dr state, the id register is unaffected. bypass (1111) the bypass instruction connects a 1 bit shift register (the bypass register) between tdi and td o. when the bypass instruction is lo aded into the instruction register, all the boundary-scan cells are placed in their normal (system) mode of operation. this instruction has no effect on the system pins. in the capture-dr state, a logic 0 is captured by the bypass register. in the shift-dr state, test data is shifted into the bypass register via tdi and out via tdo after a delay of one tck cycle. note that the first bit shifted out will be a zero. the bypass register is not affected in the update-dr state.
debug and test interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 323 - 10.3.5 test data register device id register instruction decoder bypass register instruction register HMS30C7210 core logic tap controller ntdoen tdo tdi tms tck ntrst bsincell bsoutcell bsoutcell i/o cell bsinencell bsincell bsoutencell figure 10-2. boundary scan block diagram bypass register purpose: this is a single bit register which can be selected as the path between tdi and tdo to allow the device to be bypassed during boundary-scan testing. length: 1 bit operating mode: when the bypass instruction is the current instruction in the instruction register, serial data is transferred from tdi to tdo in the shift-dr state with a delay of one tck cycle. there is no parallel output from the bypass register. a logic 0 is loaded from the parallel input of the bypass register in the capture-dr state.
debug and test interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 324 - boundary scan (bs) register purpose: the bs register consists of a serially connected set of cells around the periphery of the device, at the interface between the core logic and the system input/output pads. this register can be used to isolate the core logic from the pins and then apply tests to the core logic, or conversely to isolate the pins from the core logic and then drive or monitor the system pins. operating modes: the bs register is selected as the register to be connected between tdi and tdo only during the sample/preload, extest and intest instructions. values in the bs register are used, but are not changed, during the clamp and clampz instructions. in the normal (system) mode of operation, straight-through connections between the core logic and pins are maintained and normal system operation is unaffected. in test mode (i.e. when either extest or intest is the currently selected instruction), values can be applied to the core logic or output pins independently of the actual values on the input pins and core logic outputs respectively. on the hms30c7202 all of the boundary scan cells include an update register and thus all of the pins can be controlled in the above manner. additional boundary-scan cells are interposed in the scan chain in order to control the enabling of tristateable buses. the values stored in the bs register after power-up are not defined. similarly, the values previously clocked into the bs register are not guaranteed to be maintained across a boundary scan reset (from forcing ntrst low or entering the test logic reset state). single-step operation HMS30C7210 is a static design and there is no minimum clock speed. it can therefore be single-stepped while the intest instruction is selected and the plls are bypassed. this can be achieved by serializing a parallel stimulus and clocking the resulting serial vectors into the boundary-scan register. w hen the boundary-scan register is updated, new test stimuli are applied to the core logic inputs; the effect of these stimuli can then be observed on the core logic outputs by capturing them in the boundary-scan register.
debug and test interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 325 - 10.3.6 boundary scan interface signals figure 10-3. boundary scan general timing figure 10-4. boundary scan tri-state timing
debug and test interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 326 - figure 10-5. boundary scan reset timing symbol parameter min max tbscl tck low period 50 - tbsch tck high period 50 - tbsis tms, tdi setup to tckr 0 - tbsih tms, tdi hold from tckr 2 - tbsoh tdo output hold from tckf 3 - tbsod tdo output delay from tckf - 20 tbsss test mode data in setup to tckr 2 - tbssh test mode data in hold from tckf 5 - tbsdh test mode data out hold from tckf 3 - tbsdd test mode data out delay from tckf - 20 tbsoe tdo output enable delay from tckf 2 15 tbsoz test mode data enable delay from tckf 2 15 tbsde tdo output disable delay from tckf 2 15 tbsdz test mode data disable delay from tckf 2 15 tbsr ntrst minimun pulse width 25 - tbsrs tms setup to ntrstr 20 - tbsrh tms hold from ntrstr 20 - the ac parameters are based on simulation results using 0.0pf circuit signal loads. delays should be calculated using manufacturers output derating values for the actual circuit capacitance loading.
debug and test interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 327 - the correspondence between boundary-scan cells and system pins, system direction controls and system output enables is shown below. the cells are listed in the order in which they are connected in the boundary-scan register, starting with the cell closest to tdi. all outputs are three-state ou tputs. all boundary-scan register cells at input pins can apply tests to the on-chip system logic. extest/clamp guard values specified in the table below should be clocked into the boundary-scan register (using the sample/preload instruction) before the extest, clamp or clampz instructions are selected to ensure that known data is applied to the system logic during the test. the intest guard values shown in the table below should be clocked into the boundary-scan register (using the sample/preload instruction) before the intest instruction is selected to ensure that all outputs are disabled. an asterisk in the guard value column indicates that any value can be submitted (as test requires), but ones and zeros should always be placed as shown.
debug and test interface magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) - 328 -
electrical characteristics magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) i 11 electrical characteristics 11.1 absolute maximum ratings symbol parameter typical units vdd condition p run run mode power 391 mw @ 3.3v p slow slow mode power 355 mw @ 3.3v p idle idle mode power 276 mw @ 3.3v p pd deep-sleep mode power 3.3 uw @ 3.3v p rtc rtc power 36 uw @ 3.0v table 11-1. maximum ratings ? core / io / analog vdd are 3.3v ? operating frequency is 60mhz. ? in run/slow mode cpu generated image pattern (on sdram) and displayed to 640x480 color stn lcd (8bpp). in slow mode cpu runs with ?half clock speed? (bus clock). ? idle mode went to idle state from lcd sdram loop. ? rtc power is independent. rtc can be operated in system power off mode. at this time rtc power is connected to a battery (3.0v). ? run / slow / idle / deepsleep power consumption is estimated without rtc power dissipation. recommended operating range symbol parameter min max units vdd (3.3v) vdd (3.3v) t opr dc power supply voltage (3.3v) ? use for i/o dc power supply voltage (3.3v) ? use for a core operating temperature (industrial temperature) 3.0 3.0 -40 3.6 3.6 85 v v table 11-2. operating range
electrical characteristics magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) ii 11.2 dc characteristics all characteristics are specified at vdd=3. 0 to 3.6 volts ans vss=0 volts, over an operating temperature range of 0 to 100 c cmos pins 0 100 conditions symbol parameter min max vdd v il low-level input voltage -0.5v 0.3xvdd 2.7v to 3.6v guaranteed input low voltage v ih high-level input voltage 0.7xvdd vdd+0.5v 2.7v to 3.6v guaranteed input high voltage v ol low-level output voltage - vss+0.1v 2.7v iol = 0.8ma v oh high-level output voltage vdd?0.1v - 2.7v ioh = 0.8ma i i input current at maximum voltage - 1ma 2.7v to 3.6v input = 5.5v table 11-3. cmos signal pin characteristics ttl compatible pin 0 100 conditions symbol parameter min max vdd v il low-level input voltage -0.5v 0.8v 2.7v to 3.6v guaranteed input low voltage v ih high-level input voltage 2.0v vdd+0.5v 2.7v to 3.6v guaranteed input high voltage v ol low-level output voltage - 0.4v 2.7v iol,2 to 0.8ma depending on cell v oh high-level output voltage 2.4v - 2.7v ioh,2 to 0.8ma depending on cell i i input current at maximum voltage - 1ma 2.7v to 3.6v input = 5.5v table 11-4. ttl signal pin characteristics i/o circuit pull-up pin the following current values are used for i/os with internal pull-up devices. min current (at pad = 0v) max current (at pad = 0v) 3.3v pull-up -30ua -146ua equivalent resistance 88.3k ohms 22.6k ohms i/o circuit pull-down pin the following current values are used for i/os with internal pull-down devices. min current (at pad = 2.65v) max current (at pad = 3.6v) 3.3v pull-down 31ua 159ua equivalent resistance 85.5k ohms 22.6k ohms
electrical characteristics magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) iii 11.3 a/d converter electrical characteristics symbol paramter test condition minimum typical maximum unit normal aclk = 3.704mhz input = avref fin = 4khz ramp 4.0 ma i dd power down aclk = 3.704mhz 40 ua an* analog input voltage avss avref v accuracy resolution 10 bits inl integral non-linearity aclk = 3.704mhz input = 0-avref(v) (fin = 4khz ramp) 2.0 lsb dnl differential non-linearity aclk = 3.704mhz input = 0-avref(v) (fin = 4khz ramp) 1 .0 lsb snr signal-to-noise ratio fsample = 231.5ksps fin = 4khz 50 54 db sndr signal-to-noise distortion ratio 48 52 db aclk 3.704 mhz t c conversion time 1 4 8 us avref* analog reference voltage avdd v t cal power-up time calibration time 1.2 ms thd total harmonic distortion 50 54 db avdd* analog power 3.0 3.3 3.6 v dvdd digital power 3.0 3.3 3.6 v fin analog input frequency 60 khz table 11-5. a/d converter characteristics ? avss an0~3 avref avdd
electrical characteristics magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) iv
appendix magnachip semiconductor ltd. HMS30C7210 datasheet (ds-07) i 12 appendix the method of clearing status register peri. name register name width address method of clearing pmu pmursr 27 0x8001.0020 write ?1? *lcd lcdstatus 4 0x8005.2004 write ?1? intc status 29 0x8005.0008 clear interrupt source usb intstat 20 0x8005.100c write ?1? adcif adcisr 3 0x8005.3010 write ?1? lsr 8 uxbase+0x14 **uart(smart card) msr 8 uxbase+0x18 read register ***ssi sspsr 5 ssibase+0x0c write ?1? smc smcstat 32 0x8005.c01c write ?0? topstat 4 0x8005.d084 timer t(0/1/2/3)stat 1 0x8005.d0(0/2/4/6)c write ?1? watchdog timer wdtstat 2 0x8005.e004 read register rtc rtcstat 3 0x8005.f004 write ?1? 2wsi statusreg 16 0x8006.0008 write ?1? matrix kbd kbsr 1 0x8006.1018 write ?1? * lcd (method of clearing) ? reference : 9.1.2.2 lcd controller status/mask and interrupt registers (lcdstatus, lcdstatusm, and lcdinterrupt) ? lcdstatus[3] : write anything at lcddbar register or enable lcden signal at lcd control register[0] ? lcdstatus[2] : write ?1? ? lcdstatus[1] : write anything at lcddbar register ? lcdstatus[0] : write ?1? ** uart (address) ? uxbase : 0x8005.4000 (uart0), 0x8005.5000 (uart1), 0x8005.6000 (uart2), 0x8005.7000 (uart3), ? 0x8005.8000 (uart4), 0x8005.9000 (uart5) *** ssi (address) ? ssibase: 0x8005.a000 (ssi0), 0x8005.b000(ssi1)

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